| /Linux-v5.4/Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
17 register group access) and "bus" (required for
18 the IOMMUs underlying bus access).
20 - clocks : Phandles for respective clocks described by
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| D | arm,smmu.txt | 12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
20 "qcom,smmu-v2"
25 Qcom SoCs must contain, as below, SoC-specific compatibles
26 along with "qcom,smmu-v2":
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| D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | arm,smmu-v3.txt | 4 revisions, replacing the MMIO register interface with in-memory command
10 - compatible : Should include:
12 * "arm,smmu-v3" for any SMMUv3 compliant
16 - reg : Base address and size of the SMMU.
18 - interrupts : Non-secure interrupt list describing the wired
20 interrupt-names. If no wired interrupts are
23 - interrupt-names : When the interrupts property is present, should
25 * "eventq" - Event Queue not empty
26 * "priq" - PRI Queue not empty
27 * "cmdq-sync" - CMD_SYNC complete
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| /Linux-v5.4/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
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| D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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| D | arm,scmi.txt | 2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi"
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
31 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
40 Each protocol supported shall have a sub-node with corresponding compatible
43 mboxes, mbox-names and shmem shall be present in the sub-node corresponding
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| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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| /Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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| /Linux-v5.4/drivers/perf/ |
| D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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| /Linux-v5.4/Documentation/driver-api/ |
| D | vfio.rst | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
10 agnostic framework for exposing direct device access to userspace, in
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
15 access ("device assignment") when configured for the highest possible
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
28 and requires root privileges to access things like PCI configuration
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| /Linux-v5.4/drivers/iommu/ |
| D | arm-smmu-impl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
73 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
76 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
77 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
79 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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| D | ipmmu-vmsa.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
34 #define arm_iommu_attach_device(...) -ENODEV
40 #define IPMMU_CTX_INVALID -1
91 return fwspec ? fwspec->iommu_priv : NULL; in to_ipmmu()
96 /* -----------------------------------------------------------------------------
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| /Linux-v5.4/drivers/rtc/ |
| D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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| /Linux-v5.4/drivers/mailbox/ |
| D | ti-msgmgr.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
21 #include <linux/soc/ti/ti-msgmgr.h>
23 #define Q_DATA_OFFSET(proxy, queue, reg) \ argument
24 ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
29 #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ argument
30 (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
40 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
52 * struct ti_msgmgr_desc - Description of message manager integration
62 * @valid_queues: List of Valid queues that the processor can access
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| /Linux-v5.4/drivers/crypto/caam/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | dra7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
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| D | omap3-tao3530.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
6 /dts-v1/;
10 /* Secure omaps have some devices inaccessible depending on the firmware */
22 cpu0-supply = <&vcc>;
28 reg = <0x80000000 0x10000000>; /* 256 MB */
33 compatible = "regulator-fixed";
34 regulator-name = "hsusb2_vbus";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
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| D | imx6q-bx50v3.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
43 #include "imx6q-ba16.dtsi"
46 mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <22000000>;
52 gpio-poweroff {
53 compatible = "gpio-poweroff";
58 reg_wl18xx_vmmc: regulator-wl18xx {
59 compatible = "regulator-fixed";
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| /Linux-v5.4/arch/arm/mach-imx/ |
| D | cpu-imx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
42 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
60 if (mx5_cpu_rev == -1) in mx51_revision()
71 * Dependent on link order - so the assumption is that vfp_init is called
88 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
108 if (mx5_cpu_rev == -1) in mx53_revision()
134 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
138 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
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| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | control.h | 2 * arch/arm/mach-omap2/control.h
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
22 #define OMAP242X_CTRL_REGADDR(reg) \ argument
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24 #define OMAP243X_CTRL_REGADDR(reg) \ argument
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26 #define OMAP343X_CTRL_REGADDR(reg) \ argument
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28 #define AM33XX_CTRL_REGADDR(reg) \ argument
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| D | omap4-common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/irqchip/arm-gic.h>
25 #include <asm/hardware/cache-l2x0.h>
30 #include "omap-wakeupgen.h"
36 #include "omap4-sar-layout.h"
37 #include "omap-secure.h"
64 * We need to be careful about re-ordering which can happen as a result
75 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
88 * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
103 * The work-around for this errata needs all the initiators connected
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| /Linux-v5.4/drivers/irqchip/ |
| D | irq-gic-v3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
67 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
71 * When security is enabled, non-secure priority values from the (re)distributor
75 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
80 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
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| /Linux-v5.4/arch/arm/mm/ |
| D | cache-l2x0.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
54 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) in l2c_wait_mask() argument
57 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
62 * By default, we write directly to secure registers. Platforms must
63 * override this if they are running non-secure.
65 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec() argument
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| /Linux-v5.4/drivers/crypto/inside-secure/ |
| D | safexcel.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
10 #include <linux/dma-mapping.h>
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i)); in eip197_trc_cache_setupvirt()
51 for (i = 0; i < priv->config.rings; i++) { in eip197_trc_cache_setupvirt()
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i)); in eip197_trc_cache_setupvirt()
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i)); in eip197_trc_cache_setupvirt()
55 priv->base + EIP197_FLUE_CONFIG(i)); in eip197_trc_cache_setupvirt()
57 writel(0, priv->base + EIP197_FLUE_OFFSETS); in eip197_trc_cache_setupvirt()
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET); in eip197_trc_cache_setupvirt()
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