Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
48 compatible = "arm,armv7-timer";
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
77 #address-cells = <1>;
78 #size-cells = <0>;
82 compatible = "arm,cortex-a15";
83 reg = <0>;
85 operating-points-v2 = <&cpu0_opp_table>;
88 clock-names = "cpu";
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
116 opp-supported-hw = <0xFF 0x02>;
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
123 opp-supported-hw = <0xFF 0x04>;
132 compatible = "ti,omap-infra";
134 compatible = "ti,omap5-mpu";
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
152 reg = <0x0 0x44000000 0x0 0x1000000>,
154 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
169 compatible = "simple-bus";
170 #size-cells = <1>;
171 #address-cells = <1>;
179 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
180 reg-names = "rc_dbics", "ti_conf", "config";
182 #address-cells = <3>;
183 #size-cells = <2>;
187 bus-range = <0x00 0xff>;
188 #interrupt-cells = <1>;
189 num-lanes = <1>;
190 linux,pci-domain = <0>;
193 phy-names = "pcie-phy0";
194 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
195 interrupt-map-mask = <0 0 0 7>;
196 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
200 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
202 pcie1_intc: interrupt-controller {
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <1>;
210 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
211 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
213 num-lanes = <1>;
214 num-ib-windows = <4>;
215 num-ob-windows = <16>;
218 phy-names = "pcie-phy0";
219 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
226 compatible = "simple-bus";
227 #size-cells = <1>;
228 #address-cells = <1>;
233 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
234 reg-names = "rc_dbics", "ti_conf", "config";
236 #address-cells = <3>;
237 #size-cells = <2>;
241 bus-range = <0x00 0xff>;
242 #interrupt-cells = <1>;
243 num-lanes = <1>;
244 linux,pci-domain = <1>;
247 phy-names = "pcie-phy0";
248 interrupt-map-mask = <0 0 0 7>;
249 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
253 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
254 pcie2_intc: interrupt-controller {
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <1>;
263 compatible = "mmio-sram";
264 reg = <0x40300000 0x80000>;
266 #address-cells = <1>;
267 #size-cells = <1>;
270 * region for use by secure software. The size
277 * from the board dts file for the secure platform.
279 sram-hs@0 {
280 compatible = "ti,secure-ram";
281 reg = <0x0 0x0>;
293 compatible = "mmio-sram";
294 reg = <0x40400000 0x100000>;
296 #address-cells = <1>;
297 #size-cells = <1>;
302 compatible = "mmio-sram";
303 reg = <0x40500000 0x100000>;
305 #address-cells = <1>;
306 #size-cells = <1>;
310 reg = <0x4a0021e0 0xc
316 compatible = "ti,dra752-bandgap";
318 #thermal-sensor-cells = <1>;
323 reg = <0x40d00000 0x100>;
327 compatible = "ti,dra7-iodelay";
328 reg = <0x4844a000 0x0d1c>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 #pinctrl-cells = <2>;
335 compatible = "ti,edma3-tpcc";
337 reg = <0x43300000 0x100000>;
338 reg-names = "edma3_cc";
342 interrupt-names = "edma3_ccint", "edma3_mperr",
344 dma-requests = <64>;
345 #dma-cells = <2>;
351 * ti,edma-memcpy-channels = <20 21>;
358 compatible = "ti,edma3-tptc";
360 reg = <0x43400000 0x100000>;
362 interrupt-names = "edma3_tcerrint";
366 compatible = "ti,edma3-tptc";
368 reg = <0x43500000 0x100000>;
370 interrupt-names = "edma3_tcerrint";
374 compatible = "ti,omap5-dmm";
375 reg = <0x4e000000 0x800>;
381 compatible = "ti,dra7-dsp-iommu";
382 reg = <0x40d01000 0x100>;
385 #iommu-cells = <0>;
386 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
391 compatible = "ti,dra7-dsp-iommu";
392 reg = <0x40d02000 0x100>;
395 #iommu-cells = <0>;
396 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
401 compatible = "ti,dra7-iommu";
402 reg = <0x58882000 0x100>;
405 #iommu-cells = <0>;
406 ti,iommu-bus-err-back;
411 compatible = "ti,dra7-iommu";
412 reg = <0x55082000 0x100>;
415 #iommu-cells = <0>;
416 ti,iommu-bus-err-back;
420 abb_mpu: regulator-abb-mpu {
421 compatible = "ti,abb-v3";
422 regulator-name = "abb_mpu";
423 #address-cells = <0>;
424 #size-cells = <0>;
426 ti,settling-time = <50>;
427 ti,clock-cycles = <16>;
429 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
432 reg-names = "setup-address", "control-address",
433 "int-address", "efuse-address",
434 "ldo-address";
435 ti,tranxdone-status-mask = <0x80>;
437 ti,ldovbb-override-mask = <0x400>;
439 ti,ldovbb-vset-mask = <0x1F>;
453 abb_ivahd: regulator-abb-ivahd {
454 compatible = "ti,abb-v3";
455 regulator-name = "abb_ivahd";
456 #address-cells = <0>;
457 #size-cells = <0>;
459 ti,settling-time = <50>;
460 ti,clock-cycles = <16>;
462 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
465 reg-names = "setup-address", "control-address",
466 "int-address", "efuse-address",
467 "ldo-address";
468 ti,tranxdone-status-mask = <0x40000000>;
470 ti,ldovbb-override-mask = <0x400>;
472 ti,ldovbb-vset-mask = <0x1F>;
486 abb_dspeve: regulator-abb-dspeve {
487 compatible = "ti,abb-v3";
488 regulator-name = "abb_dspeve";
489 #address-cells = <0>;
490 #size-cells = <0>;
492 ti,settling-time = <50>;
493 ti,clock-cycles = <16>;
495 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
498 reg-names = "setup-address", "control-address",
499 "int-address", "efuse-address",
500 "ldo-address";
501 ti,tranxdone-status-mask = <0x20000000>;
503 ti,ldovbb-override-mask = <0x400>;
505 ti,ldovbb-vset-mask = <0x1F>;
519 abb_gpu: regulator-abb-gpu {
520 compatible = "ti,abb-v3";
521 regulator-name = "abb_gpu";
522 #address-cells = <0>;
523 #size-cells = <0>;
525 ti,settling-time = <50>;
526 ti,clock-cycles = <16>;
528 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
531 reg-names = "setup-address", "control-address",
532 "int-address", "efuse-address",
533 "ldo-address";
534 ti,tranxdone-status-mask = <0x10000000>;
536 ti,ldovbb-override-mask = <0x400>;
538 ti,ldovbb-vset-mask = <0x1F>;
553 compatible = "ti,dra7xxx-qspi";
554 reg = <0x4b300000 0x100>,
556 reg-names = "qspi_base", "qspi_mmap";
557 syscon-chipselects = <&scm_conf 0x558>;
558 #address-cells = <1>;
559 #size-cells = <0>;
562 clock-names = "fck";
563 num-cs = <4>;
570 compatible = "snps,dwc-ahci";
571 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
574 phy-names = "sata-phy";
577 ports-implemented = <0x1>;
583 compatible = "ti,am3352-gpmc";
585 reg = <0x50000000 0x37c>; /* device IO registers */
588 dma-names = "rxtx";
589 gpmc,num-cs = <8>;
590 gpmc,num-waitpins = <2>;
591 #address-cells = <2>;
592 #size-cells = <1>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 gpio-controller;
596 #gpio-cells = <2>;
601 compatible = "ti,irq-crossbar";
602 reg = <0x4a002a48 0x130>;
603 interrupt-controller;
604 interrupt-parent = <&wakeupgen>;
605 #interrupt-cells = <3>;
606 ti,max-irqs = <160>;
607 ti,max-crossbar-sources = <MAX_SOURCES>;
608 ti,reg-size = <2>;
609 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
610 ti,irqs-skip = <10 133 139 140>;
611 ti,irqs-safe-map = <0>;
615 compatible = "ti,dra7-dss";
616 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
621 syscon-pll-ctrl = <&scm_conf 0x538>;
622 #address-cells = <1>;
623 #size-cells = <1>;
627 compatible = "ti,dra7-dispc";
628 reg = <0x58001000 0x1000>;
632 clock-names = "fck";
634 syscon-pol = <&scm_conf 0x534>;
638 compatible = "ti,dra7-hdmi";
639 reg = <0x58040000 0x200>,
643 reg-names = "wp", "pll", "phy", "core";
649 clock-names = "fck", "sys_clk";
651 dma-names = "audio_tx";
656 compatible = "ti,omap4-aes";
658 reg = <0x4b500000 0xa0>;
661 dma-names = "tx", "rx";
663 clock-names = "fck";
667 compatible = "ti,omap4-aes";
669 reg = <0x4b700000 0xa0>;
672 dma-names = "tx", "rx";
674 clock-names = "fck";
678 compatible = "ti,omap4-des";
680 reg = <0x480a5000 0xa0>;
683 dma-names = "tx", "rx";
685 clock-names = "fck";
689 compatible = "ti,omap5-sham";
691 reg = <0x4b101000 0x300>;
694 dma-names = "rx";
696 clock-names = "fck";
699 opp_supply_mpu: opp-supply@4a003b20 {
700 compatible = "ti,omap5-opp-supply";
701 reg = <0x4a003b20 0xc>;
702 ti,efuse-settings = <
708 ti,absolute-max-voltage-uv = <1500000>;
713 thermal_zones: thermal-zones {
714 #include "omap4-cpu-thermal.dtsi"
715 #include "omap5-gpu-thermal.dtsi"
716 #include "omap5-core-thermal.dtsi"
717 #include "dra7-dspeve-thermal.dtsi"
718 #include "dra7-iva-thermal.dtsi"
724 polling-delay = <500>; /* milliseconds */
764 #include "dra7-l4.dtsi"
765 #include "dra7xx-clocks.dtsi"