Lines Matching +full:secure +full:- +full:reg +full:- +full:access
12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
20 "qcom,smmu-v2"
25 Qcom SoCs must contain, as below, SoC-specific compatibles
26 along with "qcom,smmu-v2":
27 "qcom,msm8996-smmu-v2", "qcom,smmu-v2",
28 "qcom,sdm845-smmu-v2", "qcom,smmu-v2".
30 Qcom SoCs implementing "arm,mmu-500" must also include,
31 as below, SoC-specific compatibles:
32 "qcom,sdm845-smmu-500", "arm,mmu-500"
34 - reg : Base address and size of the SMMU.
36 - #global-interrupts : The number of global interrupts exposed by the
39 - interrupts : Interrupt list, with the first #global-irqs entries
48 - #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
61 - dma-coherent : Present if page table walks made by the SMMU are
67 - calxeda,smmu-secure-config-access : Enable proper handling of buggy
68 implementations that always use secure access to
69 SMMU configuration registers. In this case non-secure
70 aliases of secure registers have to be used during
73 - stream-match-mask : For SMMUs supporting stream matching and using
74 #iommu-cells = <1>, specifies a mask of bits to ignore
78 portion of every Stream ID (e.g. for certain MMU-500
81 or using stream matching with #iommu-cells = <2>, and
84 - clock-names: List of the names of clocks input to the device. The
87 - for "qcom,smmu-v2":
88 - "bus": clock required for downstream bus access and
90 - "iface": clock required to access smmu's registers
92 - unspecified for other implementations.
94 - clocks: Specifiers for all clocks listed in the clock-names property,
97 - power-domains: Specifiers for power domains required to be powered on for
102 - mmu-masters (deprecated in favour of the generic "iommus" binding) :
106 linked from this list must have a "#stream-id-cells"
114 compatible = "arm,smmu-v1";
115 reg = <0xba5e0000 0x10000>;
116 #global-interrupts = <2>;
123 #iommu-cells = <1>;
136 #iommu-cells = <2>;
151 /* ARM MMU-500 with 10-bit stream ID input configuration */
153 compatible = "arm,mmu-500", "arm,smmu-v2";
155 #iommu-cells = <1>;
156 /* always ignore appended 5-bit TBU number */
157 stream-match-mask = 0x7c00;
161 /* bus whose child devices emit one unique 10-bit stream
163 iommu-map = <0 &smmu3 0 0x400>;
167 /* Qcom's arm,smmu-v2 implementation */
169 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
170 reg = <0xd00000 0x10000>;
172 #global-interrupts = <1>;
176 #iommu-cells = <1>;
177 power-domains = <&mmcc MDSS_GDSC>;
181 clock-names = "bus", "iface";