Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
28 * For 32-bit operations on 64-bit values, CAAM follows the same
29 * 64-bit register access conventions as it's predecessors, in that
31 * higher address, thus, a full 64-bit write cycle requires a write
37 * - SWRST is in bit 31 of MCFG.
38 * - MCFG begins at base+0x0000.
39 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
40 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
42 * (and on Power, the convention is 0-31, 32-63, I know...)
44 * Assuming a 64-bit write to this MCFG to perform a software reset
49 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
51 * However, since CAAM does contain some write-and-read-intended
52 * 64-bit registers, this code defines 64-bit access methods for
54 * clean transition to 64-bit is possible when it becomes necessary.
57 * 32-bit architectures cannot enforce an atomic-64 operation,
60 * - On writes, since the HW is assumed to latch the cycle on the
61 * write of the higher-numeric-address word, then ordered
64 * - For reads, where a register contains a relevant value of more
101 static inline void wr_reg32(void __iomem *reg, u32 data) in wr_reg32() argument
104 iowrite32(data, reg); in wr_reg32()
106 iowrite32be(data, reg); in wr_reg32()
109 static inline u32 rd_reg32(void __iomem *reg) in rd_reg32() argument
112 return ioread32(reg); in rd_reg32()
114 return ioread32be(reg); in rd_reg32()
117 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) in clrsetbits_32() argument
120 iowrite32((ioread32(reg) & ~clear) | set, reg); in clrsetbits_32()
122 iowrite32be((ioread32be(reg) & ~clear) | set, reg); in clrsetbits_32()
132 * base + 0x0000 : most-significant 32 bits
133 * base + 0x0004 : least-significant 32 bits
135 * The 32-bit version of this core therefore has to write to base + 0x0004
136 * to set the 32-bit wide DMA address.
139 * base + 0x0000 : least-significant 32 bits
140 * base + 0x0004 : most-significant 32 bits
142 static inline void wr_reg64(void __iomem *reg, u64 data) in wr_reg64() argument
146 iowrite32(data >> 32, (u32 __iomem *)(reg)); in wr_reg64()
147 iowrite32(data, (u32 __iomem *)(reg) + 1); in wr_reg64()
149 iowrite64(data, reg); in wr_reg64()
152 iowrite64be(data, reg); in wr_reg64()
156 static inline u64 rd_reg64(void __iomem *reg) in rd_reg64() argument
162 high = ioread32(reg); in rd_reg64()
163 low = ioread32(reg + sizeof(u32)); in rd_reg64()
167 return ioread64(reg); in rd_reg64()
170 return ioread64be(reg); in rd_reg64()
276 /* Version registers (Era 10+) e80-eff */
317 /* CHA Miscellaneous Information - AESA_MISC specific */
321 * caam_perfmon - Performance Monitor/Secure Memory Status/
324 * Spans f00-fff wherever instantiated
387 /* Performance Monitor Registers f00-f9f */
388 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
389 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
390 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
391 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
392 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
393 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
397 /* CAAM Hardware Instantiation Parameters fa0-fbf */
398 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
399 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
408 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
409 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
412 /* CAAM Global Status fc0-fdf */
413 u64 faultaddr; /* FAR - Fault Address */
414 u32 faultliodn; /* FALR - Fault Address LIODN */
415 u32 faultdetail; /* FADR - Fault Addr Detail */
419 u32 status; /* CSTA - CAAM Status */
422 /* Component Instantiation Parameters fe0-fff */
423 u32 rtic_id; /* RVID - RTIC Version ID */
426 u32 ccb_id; /* CCBVID - CCB Version ID */
427 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
428 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
429 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
430 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
435 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
436 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
445 u32 liodn_ms; /* lock and make-trusted control bits */
446 u32 liodn_ls; /* LIODN for non-sequence and seq access */
458 u32 mode; /* RTSTMODEx - Test mode */
460 u32 reset; /* RTSTRESETx - Test reset control */
462 u32 status; /* RTSTSSTATUSx - Test status */
464 u32 errstat; /* RTSTERRSTATx - Test error status */
466 u32 errctl; /* RTSTERRCTLx - Test error control */
468 u32 entropy; /* RTSTENTROPYx - Test entropy */
470 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
472 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
474 u32 verifdata; /* RTSTVERIFDx - Test verification data */
476 u32 xkey; /* RTSTXKEYx - Test XKEY */
478 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
480 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
482 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
484 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
490 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
534 * caam_ctrl - basic core configuration
550 /* Basic Configuration Section 000-01f */
557 /* Bus Access Configuration Section 010-11f */
559 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
561 u32 jrstart; /* JRSTART - Job Ring Start Register */
562 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
564 u32 deco_rsr; /* DECORSR - Deco Request Source */
566 u32 deco_rq; /* DECORR - DECO Request */
567 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
570 /* DECO Availability/Reset Section 120-3ff */
571 u32 deco_avail; /* DAR - DECO availability */
572 u32 deco_reset; /* DRR - DECO reset */
575 /* Key Encryption/Decryption Configuration 400-5ff */
576 /* Read/Writable only while in Non-secure mode */
577 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
578 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
579 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
581 u64 sknonce; /* SKNR - Secure Key Nonce */
584 /* RNG Test/Verification/Debug Access 600-7ff */
593 /* Version registers - introduced with era 10 e80-eff */
595 /* Performance Monitor f00-fff */
604 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
606 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
609 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
612 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
633 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */
634 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */
643 * caam_job_ring - direct job ring setup
644 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
649 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
651 u32 inpring_size; /* IRSx - Input ring size */
653 u32 inpring_avail; /* IRSAx - Input ring room remaining */
655 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
658 u64 outring_base; /* ORBAx - Output status ring base addr */
660 u32 outring_size; /* ORSx - Output ring size */
662 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
664 u32 outring_used; /* ORSFx - Output ring slots full */
668 u32 jroutstatus; /* JRSTAx - JobR output status */
670 u32 jrintstatus; /* JRINTx - JobR interrupt status */
671 u32 rconfig_hi; /* JRxCFG - Ring configuration */
676 u32 inp_rdidx; /* IRRIx - Input ring read index */
678 u32 out_wtidx; /* ORWIx - Output ring write index */
682 u32 jrcommand; /* JRCRx - JobR command */
686 /* Version registers - introduced with era 10 e80-eff */
688 /* Performance Monitor f00-fff */
694 * jrstatus - Job Ring Output Status
813 * caam_assurance - Assurance Controller View
835 u32 status; /* RSTA - Status */
837 u32 cmd; /* RCMD - Command */
839 u32 ctrl; /* RCTL - Control */
841 u32 throttle; /* RTHR - Throttle */
843 u64 watchdog; /* RWDOG - Watchdog Timer */
845 u32 rend; /* REND - Endian corrections */
848 /* Block access/configuration @ 100/110/120/130 */
849 struct rtic_block memblk[4]; /* Memory Blocks A-D */
853 struct rtic_memhash hash[4]; /* Block hash values A-D */
858 * caam_queue_if - QI configuration and control
863 u32 qi_control_hi; /* QICTL - QI Control */
866 u32 qi_status; /* QISTA - QI Status */
867 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
869 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
874 /* QI control bits - low word */
879 /* QI control bits - high word */
908 /* deco_sg_table - DECO view of scatter/gather table */
911 u32 elen; /* E, F bits + 30-bit length */
912 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
916 * caam_deco - descriptor controller - CHA cluster block
918 * Only accessible when direct DECO access is turned on
926 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
928 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
929 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
932 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
934 u32 cha_ctrl; /* CCTLR - CHA control */
936 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
938 u32 clr_written; /* CxCWR - Clear-Written */
939 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
942 u32 aad_size; /* CxAADSZR - Current AAD Size */
944 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
946 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
948 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
950 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
952 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
954 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
956 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
958 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
960 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
961 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
964 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
966 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
968 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
970 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
973 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
975 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
977 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
979 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
981 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
984 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
985 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
987 u64 math[4]; /* DxMTH - Math register */
989 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
991 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
993 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
998 u32 desc_dbg; /* DxDDR - DECO Debug Register */
1002 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */