1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
67  * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
71  * When security is enabled, non-secure priority values from the (re)distributor
75  * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
80  * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
82  * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
85  * For now, we only support pseudo-NMIs if we have non-secure view of
98 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
133 	return __get_intid_range(d->hwirq);  in get_intid_range()
138 	return d->hwirq;  in gic_irq()
152 		/* SGI+PPI -> SGI_base for this CPU */  in gic_dist_base()
157 		/* SPI -> dist_base */  in gic_dist_base()
170 		count--;  in gic_do_wait_for_rwp()
228 	while (--count) {  in gic_enable_redist()
248 		*index = d->hwirq;  in convert_offset_index()
256 		*index = d->hwirq - EPPI_BASE_INTID + 32;  in convert_offset_index()
259 		*index = d->hwirq - ESPI_BASE_INTID;  in convert_offset_index()
288 	*index = d->hwirq;  in convert_offset_index()
363 	u32 reg;  in gic_irq_set_irqchip_state()  local
365 	if (d->hwirq >= 8192) /* PPI/SPI only */  in gic_irq_set_irqchip_state()
366 		return -EINVAL;  in gic_irq_set_irqchip_state()
370 		reg = val ? GICD_ISPENDR : GICD_ICPENDR;  in gic_irq_set_irqchip_state()
374 		reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;  in gic_irq_set_irqchip_state()
378 		reg = val ? GICD_ICENABLER : GICD_ISENABLER;  in gic_irq_set_irqchip_state()
382 		return -EINVAL;  in gic_irq_set_irqchip_state()
385 	gic_poke_irq(d, reg);  in gic_irq_set_irqchip_state()
392 	if (d->hwirq >= 8192) /* PPI/SPI only */  in gic_irq_get_irqchip_state()
393 		return -EINVAL;  in gic_irq_get_irqchip_state()
409 		return -EINVAL;  in gic_irq_get_irqchip_state()
429 		return d->hwirq - 16;  in gic_get_ppi_index()
431 		return d->hwirq - EPPI_BASE_INTID + 16;  in gic_get_ppi_index()
439 	struct irq_desc *desc = irq_to_desc(d->irq);  in gic_irq_nmi_setup()
442 		return -EINVAL;  in gic_irq_nmi_setup()
445 		pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);  in gic_irq_nmi_setup()
446 		return -EINVAL;  in gic_irq_nmi_setup()
454 		return -EINVAL;  in gic_irq_nmi_setup()
463 			desc->handle_irq = handle_percpu_devid_fasteoi_nmi;  in gic_irq_nmi_setup()
466 		desc->handle_irq = handle_fasteoi_nmi;  in gic_irq_nmi_setup()
476 	struct irq_desc *desc = irq_to_desc(d->irq);  in gic_irq_nmi_teardown()
482 		pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);  in gic_irq_nmi_teardown()
499 			desc->handle_irq = handle_percpu_devid_irq;  in gic_irq_nmi_teardown()
501 		desc->handle_irq = handle_fasteoi_irq;  in gic_irq_nmi_teardown()
534 		return -EINVAL;  in gic_set_type()
541 		return -EINVAL;  in gic_set_type()
556 		pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);  in gic_set_type()
695 	 * setting the highest possible, non-zero priority in PMR.  in gic_has_group0()
699 	 * actual priority in the non-secure range. In the process, it  in gic_has_group0()
702 	 * we're don't have access to Group0.  in gic_has_group0()
704 	gic_write_pmr(BIT(8 - gic_get_pribits()));  in gic_has_group0()
723 	 * Configure SPIs as non-secure Group-1. This will only matter  in gic_dist_init()
725 	 * do the right thing if the kernel is running in secure mode,  in gic_dist_init()
767 	int ret = -ENODEV;  in gic_iterate_rdists()
773 		u32 reg;  in gic_iterate_rdists()  local
775 		reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;  in gic_iterate_rdists()
776 		if (reg != GIC_PIDR2_ARCH_GICv3 &&  in gic_iterate_rdists()
777 		    reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */  in gic_iterate_rdists()
801 	return ret ? -ENODEV : 0;  in gic_iterate_rdists()
821 		u64 offset = ptr - region->redist_base;  in __gic_populate_rdist()
823 		gic_data_rdist()->phys_base = region->phys_base + offset;  in __gic_populate_rdist()
827 			(int)(region - gic_data.redist_regions),  in __gic_populate_rdist()
828 			&gic_data_rdist()->phys_base);  in __gic_populate_rdist()
842 	WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",  in gic_populate_rdist()
845 	return -ENODEV;  in gic_populate_rdist()
915 	 * any pre-emptive interrupts from working at all). Writing a zero  in gic_cpu_sys_reg_init()
984 	 *   - The write is ignored.  in gic_cpu_sys_reg_init()
985 	 *   - The RS field is treated as 0.  in gic_cpu_sys_reg_init()
1024 	/* Configure SGIs/PPIs as non-secure Group-1 */  in gic_cpu_init()
1067 			cpu--;  in gic_compute_target_list()
1133 	void __iomem *reg;  in gic_set_affinity()  local
1143 		return -EINVAL;  in gic_set_affinity()
1146 		return -EINVAL;  in gic_set_affinity()
1154 	reg = gic_dist_base(d) + offset + (index * 8);  in gic_set_affinity()
1157 	gic_write_irouter(val, reg);  in gic_set_affinity()
1250 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1257 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1265 			return -EPERM;  in gic_irq_domain_map()
1266 		irq_domain_set_info(d, irq, hw, chip, d->host_data,  in gic_irq_domain_map()
1271 		return -EPERM;  in gic_irq_domain_map()
1284 	if (is_of_node(fwspec->fwnode)) {  in gic_irq_domain_translate()
1285 		if (fwspec->param_count < 3)  in gic_irq_domain_translate()
1286 			return -EINVAL;  in gic_irq_domain_translate()
1288 		switch (fwspec->param[0]) {  in gic_irq_domain_translate()
1290 			*hwirq = fwspec->param[1] + 32;  in gic_irq_domain_translate()
1293 			*hwirq = fwspec->param[1] + 16;  in gic_irq_domain_translate()
1296 			*hwirq = fwspec->param[1] + ESPI_BASE_INTID;  in gic_irq_domain_translate()
1299 			*hwirq = fwspec->param[1] + EPPI_BASE_INTID;  in gic_irq_domain_translate()
1302 			*hwirq = fwspec->param[1];  in gic_irq_domain_translate()
1305 			*hwirq = fwspec->param[1];  in gic_irq_domain_translate()
1306 			if (fwspec->param[1] >= 16)  in gic_irq_domain_translate()
1307 				*hwirq += EPPI_BASE_INTID - 16;  in gic_irq_domain_translate()
1312 			return -EINVAL;  in gic_irq_domain_translate()
1315 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in gic_irq_domain_translate()
1322 			fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);  in gic_irq_domain_translate()
1326 	if (is_fwnode_irqchip(fwspec->fwnode)) {  in gic_irq_domain_translate()
1327 		if(fwspec->param_count != 2)  in gic_irq_domain_translate()
1328 			return -EINVAL;  in gic_irq_domain_translate()
1330 		*hwirq = fwspec->param[0];  in gic_irq_domain_translate()
1331 		*type = fwspec->param[1];  in gic_irq_domain_translate()
1337 	return -EINVAL;  in gic_irq_domain_translate()
1378         if (fwspec->fwnode != d->fwnode)  in gic_irq_domain_select()
1382 	if (!is_of_node(fwspec->fwnode))  in gic_irq_domain_select()
1386 	 * If this is a PPI and we have a 4th (non-null) parameter,  in gic_irq_domain_select()
1389 	if (fwspec->param_count >= 4 &&  in gic_irq_domain_select()
1390 	    fwspec->param[0] == 1 && fwspec->param[3] != 0 &&  in gic_irq_domain_select()
1392 		return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);  in gic_irq_domain_select()
1413 		return -ENOMEM;  in partition_domain_translate()
1415 	np = of_find_node_by_phandle(fwspec->param[3]);  in partition_domain_translate()
1417 		return -EINVAL;  in partition_domain_translate()
1419 	ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],  in partition_domain_translate()
1425 	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in partition_domain_translate()
1439 	d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;  in gic_enable_quirk_msm8996()
1449 	 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite  in gic_enable_quirk_hip06_07()
1451 	 * that GIC-600 doesn't have ESPI, so nothing to do in that case.  in gic_enable_quirk_hip06_07()
1455 	if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {  in gic_enable_quirk_hip06_07()
1457 		d->rdists.gicd_typer &= ~GENMASK(9, 8);  in gic_enable_quirk_hip06_07()
1467 		.compatible = "qcom,msm8996-gic-v3",
1494 		pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");  in gic_enable_nmi_support()
1543 	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);  in gic_init_bases()
1553 		err = -ENOMEM;  in gic_init_bases()
1597 	u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;  in gic_validate_dist_version()  local
1599 	if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)  in gic_validate_dist_version()
1600 		return -ENODEV;  in gic_validate_dist_version()
1613 	parts_node = of_get_child_by_name(gic_node, "ppi-partitions");  in gic_populate_ppi_partitions()
1636 		part->partition_id = of_node_to_fwnode(child_part);  in gic_populate_ppi_partitions()
1665 			cpumask_set_cpu(cpu, &part->mask);  in gic_populate_ppi_partitions()
1712 	if (of_property_read_u32(node, "#redistributor-regions",  in gic_of_setup_kvm_info()
1736 		return -ENXIO;  in gic_of_init()
1745 	if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))  in gic_of_init()
1751 		err = -ENOMEM;  in gic_of_init()
1763 			err = -ENODEV;  in gic_of_init()
1769 	if (of_property_read_u64(node, "redistributor-stride", &redist_stride))  in gic_of_init()
1775 			     redist_stride, &node->fwnode);  in gic_of_init()
1795 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1828 	redist_base = ioremap(redist->base_address, redist->length);  in gic_acpi_parse_madt_redist()
1830 		pr_err("Couldn't map GICR region @%llx\n", redist->base_address);  in gic_acpi_parse_madt_redist()
1831 		return -ENOMEM;  in gic_acpi_parse_madt_redist()
1834 	gic_acpi_register_redist(redist->base_address, redist_base);  in gic_acpi_parse_madt_redist()
1844 	u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;  in gic_acpi_parse_madt_gicc()  local
1845 	u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;  in gic_acpi_parse_madt_gicc()
1849 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_parse_madt_gicc()
1852 	redist_base = ioremap(gicc->gicr_base_address, size);  in gic_acpi_parse_madt_gicc()
1854 		return -ENOMEM;  in gic_acpi_parse_madt_gicc()
1856 	gic_acpi_register_redist(gicc->gicr_base_address, redist_base);  in gic_acpi_parse_madt_gicc()
1878 	return -ENODEV;  in gic_acpi_collect_gicr_base()
1898 	if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)  in gic_acpi_match_gicc()
1905 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_match_gicc()
1908 	return -ENODEV;  in gic_acpi_match_gicc()
1942 	if (dist->version != ape->driver_data)  in acpi_validate_gic_table()
1963 	if (!(gicc->flags & ACPI_MADT_ENABLED))  in gic_acpi_parse_virt_madt_gicc()
1966 	maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?  in gic_acpi_parse_virt_madt_gicc()
1972 		acpi_data.maint_irq = gicc->vgic_interrupt;  in gic_acpi_parse_virt_madt_gicc()
1974 		acpi_data.vcpu_base = gicc->gicv_base_address;  in gic_acpi_parse_virt_madt_gicc()
1982 	if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||  in gic_acpi_parse_virt_madt_gicc()
1984 	    (acpi_data.vcpu_base != gicc->gicv_base_address))  in gic_acpi_parse_virt_madt_gicc()
1985 		return -EINVAL;  in gic_acpi_parse_virt_madt_gicc()
2026 		vcpu->flags = IORESOURCE_MEM;  in gic_acpi_setup_kvm_info()
2027 		vcpu->start = acpi_data.vcpu_base;  in gic_acpi_setup_kvm_info()
2028 		vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;  in gic_acpi_setup_kvm_info()
2045 	acpi_data.dist_base = ioremap(dist->base_address,  in gic_acpi_init()
2049 		return -ENOMEM;  in gic_acpi_init()
2062 		err = -ENOMEM;  in gic_acpi_init()
2070 	domain_handle = irq_domain_alloc_fwnode(&dist->base_address);  in gic_acpi_init()
2072 		err = -ENOMEM;  in gic_acpi_init()