Searched +full:clocks +full:- +full:bindings (Results 1 – 25 of 1234) sorted by relevance
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
5 functional clock but can be configured to provide different clocks.
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and it's output clocks (which can be used
10 internally within the SoC or external components) two sets of bindings is needed:
14 To be able to integrate the ATL clocks with DT clock tree.
15 Provides ccf level representation of the ATL clocks to be used by drivers.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
23 - compatible : shall be "ti,dra7-atl-clock"
24 - #clock-cells : from common clock binding; shall be set to 0.
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| D | composite.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped composite clock with multiple different sub-types;
16 The binding must provide a list of the component clocks that shall be
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21 [2] Documentation/devicetree/bindings/clock/ti/mux.txt
22 [3] Documentation/devicetree/bindings/clock/ti/divider.txt
23 [4] Documentation/devicetree/bindings/clock/ti/gate.txt
26 - compatible : shall be: "ti,composite-clock"
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| /Linux-v5.10/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
22 See Documentation/devicetree/bindings/mailbox/mailbox.txt
24 client driver bindings.
26 Clock bindings for the clocks based on SCPI Message Protocol
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
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| D | sp810.txt | 2 -----------------------
6 - compatible: standard compatible string for a Primecell peripheral,
7 see Documentation/devicetree/bindings/arm/primecell.yaml
11 - reg: standard registers property, physical address and size
14 - clock-names: from the common clock bindings, for more details see
15 Documentation/devicetree/bindings/clock/clock-bindings.txt;
18 - clocks: from the common clock bindings, phandle and clock
19 specifier pairs for the entries of clock-names property
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
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| /Linux-v5.10/Documentation/devicetree/bindings/soc/mediatek/ |
| D | scpsys.txt | 10 The driver implements the Generic PM domain bindings described in
11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
21 - "mediatek,mt2701-scpsys"
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | maxim,max77686.txt | 3 This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4 multi-function device. More information can be found in MFD DT binding
6 bindings/mfd/max77686.txt for MAX77686 and
7 bindings/mfd/max77802.txt for MAX77802 and
8 bindings/mfd/max77620.txt for MAX77620.
11 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
12 dt-bindings/clock/maxim,max77686.h.
16 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
17 dt-bindings/clock/maxim,max77802.h.
20 (gated/ungated) over I2C. Clocks are defined as preprocessor macros in
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| D | samsung,s5pv210-clock.txt | 9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
20 All available clocks are defined as preprocessor macros in
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
26 that they are defined using standard clock bindings with following
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| D | exynos4-clock.txt | 9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
21 All available clocks are defined as preprocessor macros in
22 dt-bindings/clock/exynos4.h header and can be used in device
27 clock: clock-controller@10030000 {
28 compatible = "samsung,exynos4210-clock";
30 #clock-cells = <1>;
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| D | nvidia,tegra124-car.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 for muxing and gating Tegra's clocks, and setting their rates.
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
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| D | qcom,sc7180-lpasscorecc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm LPASS core clock control module which supports the clocks and
17 - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
22 - qcom,sc7180-lpasshm
23 - qcom,sc7180-lpasscorecc
25 clocks:
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| D | xlnx,zynqmp-clk.txt | 1 --------------------------------------------------------------------------
2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
4 --------------------------------------------------------------------------
7 as clock provider for all clock consumers of PS clocks.
9 See clock_bindings.txt for more information on the generic clock bindings.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
15 clocks to the given clock controller. Please refer
16 the next section to find the input clocks for a
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| D | samsung,s3c2412-clock.txt | 9 - compatible: should be "samsung,s3c2412-clock"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
15 to specify the clock which they consume. Some of the clocks are available only
18 All available clocks are defined as preprocessor macros in
19 dt-bindings/clock/s3c2412.h header and can be used in device
22 External clocks:
24 There are several clocks that are generated outside the SoC. It is expected
25 that they are defined using standard clock bindings with following
26 clock-output-names:
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| D | samsung,s2mps11.txt | 4 This is a part of device tree bindings for S2M and S5M family multi-function
6 More information can be found in bindings/mfd/sec-core.txt file.
11 To register these as clocks with common clock framework instantiate under
12 main device node a sub-node named "clocks".
15 - Documentation/devicetree/bindings/clock/clock-bindings.txt
18 Required properties of the "clocks" sub-node:
19 - #clock-cells: should be 1.
20 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
21 "samsung,s2mps14-clk", "samsung,s5m8767-clk"
23 clocks.
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| /Linux-v5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
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| D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
22 clocks:
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| /Linux-v5.10/Documentation/devicetree/bindings/soc/bcm/ |
| D | brcm,bcm2835-pm.txt | 4 a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt
9 - compatible: Should be "brcm,bcm2835-pm"
10 - reg: Specifies base physical address and size of the two
13 - clocks: a) v3d: The V3D clock from CPRMAN
17 - #reset-cells: Should be 1. This property follows the reset controller
18 bindings[1].
19 - #power-domain-cells: Should be 1. This property follows the power domain
20 bindings[2].
24 - timeout-sec: Contains the watchdog timeout in seconds
25 - system-power-controller: Whether the watchdog is controlling the
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| /Linux-v5.10/Documentation/devicetree/bindings/media/ |
| D | mediatek-mdp.txt | 6 - compatible: "mediatek,mt8173-mdp"
7 - mediatek,vpu: the node of video processor unit, see
8 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
11 - compatible: Should be one of
12 "mediatek,mt8173-mdp-rdma" - read DMA
13 "mediatek,mt8173-mdp-rsz" - resizer
14 "mediatek,mt8173-mdp-wdma" - write DMA
15 "mediatek,mt8173-mdp-wrot" - write DMA with rotation
16 - reg: Physical base address and length of the function block register space
17 - clocks: device clocks, see
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| /Linux-v5.10/Documentation/devicetree/bindings/display/ |
| D | ingenic,lcd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs LCD controller devicetree bindings
10 - Paul Cercueil <paul@crapouillou.net>
14 pattern: "^lcd-controller@[0-9a-f]+$"
18 - ingenic,jz4740-lcd
19 - ingenic,jz4725b-lcd
20 - ingenic,jz4770-lcd
21 - ingenic,jz4780-lcd
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| D | arm,komeda.txt | 1 Device Tree bindings for Arm Komeda display driver
4 - compatible: Should be "arm,mali-d71"
5 - reg: Physical base address and length of the registers in the system
6 - interrupts: the interrupt line number of the device in the system
7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
8 in 'clock-names'
9 - clock-names: A list of clock names. It should contain:
10 - "aclk": for the main processor clock
11 - #address-cells: Must be 1
12 - #size-cells: Must be 0
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| /Linux-v5.10/Documentation/devicetree/bindings/display/msm/ |
| D | mdp5.txt | 5 This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
6 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
11 - compatible:
12 * "qcom,mdss" - MDSS
13 - reg: Physical base address and length of the controller's registers.
14 - reg-names: The names of register regions. The following regions are required:
17 - interrupts: The interrupt signal from MDSS.
18 - interrupt-controller: identifies the node as an interrupt controller.
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - power-domains: a power domain consumer specifier according to
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| D | dpu.txt | 5 Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
16 Documentation/devicetree/bindings/power/power_domain.txt
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
19 The following clocks are required:
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| /Linux-v5.10/Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Real Time Clock Bindings
10 - Gabriel Fernandez <gabriel.fernandez@st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
22 clocks:
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| /Linux-v5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,disp.txt | 12 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
25 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
26 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
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| /Linux-v5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
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