Lines Matching +full:clocks +full:- +full:bindings
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
22 clocks:
24 description: clock-specifier to represent input to the WIZ
26 clock-names:
28 - const: fck
29 - const: core_ref_clk
30 - const: ext_ref_clk
32 num-lanes:
36 "#address-cells":
39 "#size-cells":
42 "#reset-cells":
47 assigned-clocks:
51 assigned-clock-parents:
55 assigned-clock-rates:
59 typec-dir-gpios:
62 GPIO to signal Type-C cable orientation for lane swap.
64 achieve the funtionality of an external type-C plug flip mux.
66 typec-dir-debounce-ms:
71 Number of milliseconds to wait before sampling typec-dir-gpio.
73 Type-C spec states minimum CC pin debounce of 100 ms and maximum
77 "^pll[0|1]-refclk$":
83 clocks:
87 "#clock-cells":
90 assigned-clocks:
93 assigned-clock-parents:
97 - clocks
98 - "#clock-cells"
99 - assigned-clocks
100 - assigned-clock-parents
102 "^cmn-refclk1?-dig-div$":
108 clocks:
113 "#clock-cells":
117 - clocks
118 - "#clock-cells"
120 "^refclk-dig$":
127 clocks:
133 "#clock-cells":
136 assigned-clocks:
139 assigned-clock-parents:
143 - clocks
144 - "#clock-cells"
145 - assigned-clocks
146 - assigned-clock-parents
148 "^serdes@[0-9a-f]+$":
153 bindings specified in
154 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
155 Torrent SERDES should follow the bindings specified in
156 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
159 - compatible
160 - power-domains
161 - clocks
162 - clock-names
163 - num-lanes
164 - "#address-cells"
165 - "#size-cells"
166 - "#reset-cells"
167 - ranges
172 - |
173 #include <dt-bindings/soc/ti,sci_pm_domain.h>
176 compatible = "ti,j721e-wiz-16g";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
180 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
181 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
182 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
183 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
184 num-lanes = <2>;
185 #reset-cells = <1>;
188 pll0-refclk {
189 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
190 #clock-cells = <0>;
191 assigned-clocks = <&wiz1_pll0_refclk>;
192 assigned-clock-parents = <&k3_clks 293 13>;
195 pll1-refclk {
196 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
197 #clock-cells = <0>;
198 assigned-clocks = <&wiz1_pll1_refclk>;
199 assigned-clock-parents = <&k3_clks 293 0>;
202 cmn-refclk-dig-div {
203 clocks = <&wiz1_refclk_dig>;
204 #clock-cells = <0>;
207 cmn-refclk1-dig-div {
208 clocks = <&wiz1_pll1_refclk>;
209 #clock-cells = <0>;
212 refclk-dig {
213 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
215 #clock-cells = <0>;
216 assigned-clocks = <&wiz0_refclk_dig>;
217 assigned-clock-parents = <&k3_clks 292 11>;
221 compatible = "cdns,ti,sierra-phy-t0";
222 reg-names = "serdes";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 reset-names = "sierra_reset";
228 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
229 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";