Lines Matching +full:clocks +full:- +full:bindings
9 - compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
21 All available clocks are defined as preprocessor macros in
22 dt-bindings/clock/exynos4.h header and can be used in device
27 clock: clock-controller@10030000 {
28 compatible = "samsung,exynos4210-clock";
30 #clock-cells = <1>;
34 controller. Refer to the standard clock bindings for information
35 about 'clocks' and 'clock-names' property.
38 compatible = "samsung,exynos4210-uart";
41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
42 clock-names = "uart", "clk_uart_baud0";
45 Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
46 subsystem. Registers for those clocks are located in the ISP power domain.
53 - compatible: should be "samsung,exynos4412-isp-clock".
55 - reg: physical base address of the ISP clock controller and length of memory
58 - #clock-cells: should be 1.
60 - clocks: list of the clock controller input clock identifiers,
61 from common clock bindings, should point to CLK_ACLK200 and
62 CLK_ACLK400_MCUISP clocks from the main clock controller.
64 - clock-names: list of the clock controller input clock names,
65 as described in clock-bindings.txt, should be "aclk200" and
68 - power-domains: a phandle to ISP power domain node as described by
69 generic PM domain bindings.
71 Example 3: The clock controllers bindings for Exynos4412 SoCs.
73 clock: clock-controller@10030000 {
74 compatible = "samsung,exynos4412-clock";
76 #clock-cells = <1>;
79 isp_clock: clock-controller@10048000 {
80 compatible = "samsung,exynos4412-isp-clock";
82 #clock-cells = <1>;
83 power-domains = <&pd_isp>;
84 clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
85 clock-names = "aclk200", "aclk400_mcuisp";