Lines Matching +full:clocks +full:- +full:bindings

6 - compatible: "mediatek,mt8173-mdp"
7 - mediatek,vpu: the node of video processor unit, see
8   Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
11 - compatible: Should be one of
12         "mediatek,mt8173-mdp-rdma"  - read DMA
13         "mediatek,mt8173-mdp-rsz"   - resizer
14         "mediatek,mt8173-mdp-wdma"  - write DMA
15         "mediatek,mt8173-mdp-wrot"  - write DMA with rotation
16 - reg: Physical base address and length of the function block register space
17 - clocks: device clocks, see
18   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
19 - power-domains: a phandle to the power domain, see
20   Documentation/devicetree/bindings/power/power_domain.txt for details.
23 - compatible: Should be one of
24         "mediatek,mt8173-mdp-rdma"
25         "mediatek,mt8173-mdp-wdma"
26         "mediatek,mt8173-mdp-wrot"
27 - iommus: should point to the respective IOMMU block with master port as
28   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
30 - mediatek,larb: must contain the local arbiters in the current Socs, see
31   Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
36 		compatible = "mediatek,mt8173-mdp-rdma";
37 			     "mediatek,mt8173-mdp";
39 		clocks = <&mmsys CLK_MM_MDP_RDMA0>,
41 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
48 		compatible = "mediatek,mt8173-mdp-rdma";
50 		clocks = <&mmsys CLK_MM_MDP_RDMA1>,
52 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
58 		compatible = "mediatek,mt8173-mdp-rsz";
60 		clocks = <&mmsys CLK_MM_MDP_RSZ0>;
61 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
65 		compatible = "mediatek,mt8173-mdp-rsz";
67 		clocks = <&mmsys CLK_MM_MDP_RSZ1>;
68 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
72 		compatible = "mediatek,mt8173-mdp-rsz";
74 		clocks = <&mmsys CLK_MM_MDP_RSZ2>;
75 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
79 		compatible = "mediatek,mt8173-mdp-wdma";
81 		clocks = <&mmsys CLK_MM_MDP_WDMA>;
82 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
88 		compatible = "mediatek,mt8173-mdp-wrot";
90 		clocks = <&mmsys CLK_MM_MDP_WROT0>;
91 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
97 		compatible = "mediatek,mt8173-mdp-wrot";
99 		clocks = <&mmsys CLK_MM_MDP_WROT1>;
100 		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;