Lines Matching +full:clocks +full:- +full:bindings
5 Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
16 Documentation/devicetree/bindings/power/power_domain.txt
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
19 The following clocks are required:
23 - interrupts: interrupt signal from MDSS.
24 - interrupt-controller: identifies the node as an interrupt controller.
25 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
27 - iommus: phandle of iommu device node.
28 - #address-cells: number of address cells for the MDSS children. Should be 1.
29 - #size-cells: Should be 1.
30 - ranges: parent bus address space is the same as the child bus address space.
31 - interconnects : interconnect path specifier for MDSS according to
32 Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
34 - interconnect-names : MDSS will have 2 port names to differentiate between the
38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
44 - compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
45 - reg: physical base address and length of controller's registers.
46 - reg-names : register region names. The following region is required:
49 - clocks: list of clock specifiers for clocks needed by the device.
50 - clock-names: device clock names, must be in same order as clocks property.
51 The following clocks are required.
56 - interrupts: interrupt line from DPU to MDSS.
57 - ports: contains the list of output ports from DPU device. These ports connect
63 Documentation/devicetree/bindings/graph.txt
64 Documentation/devicetree/bindings/media/video-interfaces.txt
66 Port 0 -> DPU_INTF1 (DSI1)
67 Port 1 -> DPU_INTF2 (DSI2)
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
77 compatible = "qcom,sdm845-mdss";
79 reg-names = "mdss";
81 power-domains = <&clock_dispcc 0>;
83 clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
85 clock-names = "iface", "bus", "core";
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
91 interrupt-controller;
92 #interrupt-cells = <1>;
97 interconnect-names = "mdp0-mem", "mdp1-mem";
101 #address-cells = <2>;
102 #size-cells = <1>;
106 compatible = "qcom,sdm845-dpu";
108 reg-names = "mdp", "vbif";
110 clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
114 clock-names = "iface", "bus", "core", "vsync";
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
123 #address-cells = <1>;
124 #size-cells = <0>;
129 remote-endpoint = <&dsi0_in>;
136 remote-endpoint = <&dsi1_in>;