Lines Matching +full:clocks +full:- +full:bindings
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
20 - reset-names: Must include the following entries:
21 - host1x
23 The host1x top-level node defines a number of children, each representing one
26 - mpe: video encoder
29 - compatible: "nvidia,tegra<chip>-mpe"
30 - reg: Physical base address and length of the controller's registers.
31 - interrupts: The interrupt outputs from the controller.
32 - clocks: Must contain one entry, for the module clock.
33 See ../clocks/clock-bindings.txt for details.
34 - resets: Must contain an entry for each entry in reset-names.
36 - reset-names: Must include the following entries:
37 - mpe
39 - vi: video input
42 - compatible: "nvidia,tegra<chip>-vi"
43 - reg: Physical base address and length of the controller registers.
44 - interrupts: The interrupt outputs from the controller.
45 - clocks: clocks: Must contain one entry, for the module clock.
46 See ../clocks/clock-bindings.txt for details.
47 - Tegra20/Tegra30/Tegra114/Tegra124:
48 - resets: Must contain an entry for each entry in reset-names.
50 - reset-names: Must include the following entries:
51 - vi
52 - Tegra210:
53 - power-domains: Must include venc powergate node as vi is in VE partition.
58 ports node. Please refer to the bindings defined in
59 Documentation/devicetree/bindings/media/video-interfaces.txt
65 - csi: mipi csi interface to vi
68 - compatible: "nvidia,tegra210-csi"
69 - reg: Physical base address offset to parent and length of the controller
71 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
72 See ../clocks/clock-bindings.txt for details.
73 - power-domains: Must include sor powergate node as csicil is in
81 - reg: csi port number. Valid port numbers are 0 through 5.
82 - nvidia,mipi-calibrate: Should contain a phandle and a specifier
84 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
91 Please refer to the bindings defined in
92 Documentation/devicetree/bindings/media/video-interfaces.txt
100 - reg: 0
104 - data-lanes: an array of data lane from 1 to 4. Valid array
106 - remote-endpoint: phandle to sensor 'endpoint' node.
110 - reg: 1
114 - remote-endpoint: phandle to vi port 'endpoint' node.
116 - epp: encoder pre-processor
119 - compatible: "nvidia,tegra<chip>-epp"
120 - reg: Physical base address and length of the controller's registers.
121 - interrupts: The interrupt outputs from the controller.
122 - clocks: Must contain one entry, for the module clock.
123 See ../clocks/clock-bindings.txt for details.
124 - resets: Must contain an entry for each entry in reset-names.
126 - reset-names: Must include the following entries:
127 - epp
129 - isp: image signal processor
132 - compatible: "nvidia,tegra<chip>-isp"
133 - reg: Physical base address and length of the controller's registers.
134 - interrupts: The interrupt outputs from the controller.
135 - clocks: Must contain one entry, for the module clock.
136 See ../clocks/clock-bindings.txt for details.
137 - resets: Must contain an entry for each entry in reset-names.
139 - reset-names: Must include the following entries:
140 - isp
142 - gr2d: 2D graphics engine
145 - compatible: "nvidia,tegra<chip>-gr2d"
146 - reg: Physical base address and length of the controller's registers.
147 - interrupts: The interrupt outputs from the controller.
148 - clocks: Must contain one entry, for the module clock.
149 See ../clocks/clock-bindings.txt for details.
150 - resets: Must contain an entry for each entry in reset-names.
152 - reset-names: Must include the following entries:
153 - 2d
155 - gr3d: 3D graphics engine
158 - compatible: "nvidia,tegra<chip>-gr3d"
159 - reg: Physical base address and length of the controller's registers.
160 - clocks: Must contain an entry for each entry in clock-names.
161 See ../clocks/clock-bindings.txt for details.
162 - clock-names: Must include the following entries:
164 - 3d
166 - 3d2 (Only required on SoCs with two 3D clocks)
167 - resets: Must contain an entry for each entry in reset-names.
169 - reset-names: Must include the following entries:
170 - 3d
171 - 3d2 (Only required on SoCs with two 3D clocks)
173 - dc: display controller
176 - compatible: "nvidia,tegra<chip>-dc"
177 - reg: Physical base address and length of the controller's registers.
178 - interrupts: The interrupt outputs from the controller.
179 - clocks: Must contain an entry for each entry in clock-names.
180 See ../clocks/clock-bindings.txt for details.
181 - clock-names: Must include the following entries:
182 - dc
184 - parent
185 - resets: Must contain an entry for each entry in reset-names.
187 - reset-names: Must include the following entries:
188 - dc
189 - nvidia,head: The number of the display controller head. This is used to
196 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
197 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
198 - nvidia,edid: supplies a binary EDID blob
199 - nvidia,panel: phandle of a display panel
201 - hdmi: High Definition Multimedia Interface
204 - compatible: "nvidia,tegra<chip>-hdmi"
205 - reg: Physical base address and length of the controller's registers.
206 - interrupts: The interrupt outputs from the controller.
207 - hdmi-supply: supply for the +5V HDMI connector pin
208 - vdd-supply: regulator for supply voltage
209 - pll-supply: regulator for PLL
210 - clocks: Must contain an entry for each entry in clock-names.
211 See ../clocks/clock-bindings.txt for details.
212 - clock-names: Must include the following entries:
213 - hdmi
215 - parent
216 - resets: Must contain an entry for each entry in reset-names.
218 - reset-names: Must include the following entries:
219 - hdmi
222 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
223 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
224 - nvidia,edid: supplies a binary EDID blob
225 - nvidia,panel: phandle of a display panel
227 - tvo: TV encoder output
230 - compatible: "nvidia,tegra<chip>-tvo"
231 - reg: Physical base address and length of the controller's registers.
232 - interrupts: The interrupt outputs from the controller.
233 - clocks: Must contain one entry, for the module clock.
234 See ../clocks/clock-bindings.txt for details.
236 - dsi: display serial interface
239 - compatible: "nvidia,tegra<chip>-dsi"
240 - reg: Physical base address and length of the controller's registers.
241 - clocks: Must contain an entry for each entry in clock-names.
242 See ../clocks/clock-bindings.txt for details.
243 - clock-names: Must include the following entries:
244 - dsi
246 - lp
247 - parent
248 - resets: Must contain an entry for each entry in reset-names.
250 - reset-names: Must include the following entries:
251 - dsi
252 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
253 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
255 ../display/tegra/nvidia,tegra114-mipi.txt.
258 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
259 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
260 - nvidia,edid: supplies a binary EDID blob
261 - nvidia,panel: phandle of a display panel
262 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
265 - sor: serial output resource
268 - compatible: Should be:
269 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
270 - "nvidia,tegra132-sor": for Tegra132
271 - "nvidia,tegra210-sor": for Tegra210
272 - "nvidia,tegra210-sor1": for Tegra210
273 - "nvidia,tegra186-sor": for Tegra186
274 - "nvidia,tegra186-sor1": for Tegra186
275 - reg: Physical base address and length of the controller's registers.
276 - interrupts: The interrupt outputs from the controller.
277 - clocks: Must contain an entry for each entry in clock-names.
278 See ../clocks/clock-bindings.txt for details.
279 - clock-names: Must include the following entries:
280 - sor: clock input for the SOR hardware
281 - out: SOR output clock
282 - parent: input for the pixel clock
283 - dp: reference clock for the SOR clock
284 - safe: safe reference for the SOR clock during power up
287 - pad: SOR pad output clock (on Tegra186 and later)
290 - source: source clock for the SOR clock (obsolete, use "out" instead)
292 - resets: Must contain an entry for each entry in reset-names.
294 - reset-names: Must include the following entries:
295 - sor
298 - nvidia,interface: index of the SOR interface
301 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
302 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
303 - nvidia,edid: supplies a binary EDID blob
304 - nvidia,panel: phandle of a display panel
305 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
310 - nvidia,dpaux: phandle to a DispayPort AUX interface
312 - dpaux: DisplayPort AUX interface
313 - compatible : Should contain one of the following:
314 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
315 - "nvidia,tegra210-dpaux": for Tegra210
316 - reg: Physical base address and length of the controller's registers.
317 - interrupts: The interrupt outputs from the controller.
318 - clocks: Must contain an entry for each entry in clock-names.
319 See ../clocks/clock-bindings.txt for details.
320 - clock-names: Must include the following entries:
321 - dpaux: clock input for the DPAUX hardware
322 - parent: reference clock
323 - resets: Must contain an entry for each entry in reset-names.
325 - reset-names: Must include the following entries:
326 - dpaux
327 - vdd-supply: phandle of a supply that powers the DisplayPort link
328 - i2c-bus: Subnode where I2C slave devices are listed. This subnode
332 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
333 regarding the DPAUX pad controller bindings.
335 - vic: Video Image Compositor
336 - compatible : "nvidia,tegra<chip>-vic"
337 - reg: Physical base address and length of the controller's registers.
338 - interrupts: The interrupt outputs from the controller.
339 - clocks: Must contain an entry for each entry in clock-names.
340 See ../clocks/clock-bindings.txt for details.
341 - clock-names: Must include the following entries:
342 - vic: clock input for the VIC hardware
343 - resets: Must contain an entry for each entry in reset-names.
345 - reset-names: Must include the following entries:
346 - vic
354 compatible = "nvidia,tegra20-host1x", "simple-bus";
358 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
360 reset-names = "host1x";
362 #address-cells = <1>;
363 #size-cells = <1>;
368 compatible = "nvidia,tegra20-mpe";
371 clocks = <&tegra_car TEGRA20_CLK_MPE>;
373 reset-names = "mpe";
377 compatible = "nvidia,tegra210-vi";
380 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
381 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
383 clocks = <&tegra_car TEGRA210_CLK_VI>;
384 power-domains = <&pd_venc>;
386 #address-cells = <1>;
387 #size-cells = <1>;
392 #address-cells = <1>;
393 #size-cells = <0>;
398 remote-endpoint = <&imx219_csi_out0>;
404 compatible = "nvidia,tegra210-csi";
406 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
410 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
413 assigned-clock-rates = <102000000>,
418 clocks = <&tegra_car TEGRA210_CLK_CSI>,
423 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
424 power-domains = <&pd_sor>;
426 #address-cells = <1>;
427 #size-cells = <0>;
431 nvidia,mipi-calibrate = <&mipi 0x001>;
434 #address-cells = <1>;
435 #size-cells = <0>;
440 data-lanes = <1 2>;
441 remote-endpoint = <&imx219_out0>;
448 remote-endpoint = <&imx219_vi_in0>;
457 compatible = "nvidia,tegra20-epp";
460 clocks = <&tegra_car TEGRA20_CLK_EPP>;
462 reset-names = "epp";
466 compatible = "nvidia,tegra20-isp";
469 clocks = <&tegra_car TEGRA20_CLK_ISP>;
471 reset-names = "isp";
475 compatible = "nvidia,tegra20-gr2d";
478 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
480 reset-names = "2d";
484 compatible = "nvidia,tegra20-gr3d";
486 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
488 reset-names = "3d";
492 compatible = "nvidia,tegra20-dc";
495 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
497 clock-names = "dc", "parent";
499 reset-names = "dc";
507 compatible = "nvidia,tegra20-dc";
510 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
512 clock-names = "dc", "parent";
514 reset-names = "dc";
522 compatible = "nvidia,tegra20-hdmi";
525 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
527 clock-names = "hdmi", "parent";
529 reset-names = "hdmi";
534 compatible = "nvidia,tegra20-tvo";
537 clocks = <&tegra_car TEGRA20_CLK_TVO>;
542 compatible = "nvidia,tegra20-dsi";
544 clocks = <&tegra_car TEGRA20_CLK_DSI>,
546 clock-names = "dsi", "parent";
548 reset-names = "dsi";