| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 95 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
107 struct amdgpu_device *adev = dev->dev_private; in amdgpu_device_is_px() local
109 if (adev->flags & AMD_IS_PX) in amdgpu_device_is_px()
126 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, in amdgpu_mm_rreg() argument
131 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) in amdgpu_mm_rreg()
132 return amdgpu_virt_kiq_rreg(adev, reg); in amdgpu_mm_rreg()
134 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) in amdgpu_mm_rreg()
135 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); in amdgpu_mm_rreg()
139 spin_lock_irqsave(&adev->mmio_idx_lock, flags); in amdgpu_mm_rreg()
140 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); in amdgpu_mm_rreg()
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| D | vi.c | 84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
101 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
114 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
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| D | soc15.c | 71 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
75 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
76 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
78 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
82 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
86 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
90 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
91 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
93 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
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| D | amdgpu_ih.c | 37 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) in amdgpu_ih_ring_alloc() argument
42 if (adev->irq.ih.ring_obj == NULL) { in amdgpu_ih_ring_alloc()
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size, in amdgpu_ih_ring_alloc()
45 &adev->irq.ih.ring_obj, in amdgpu_ih_ring_alloc()
46 &adev->irq.ih.gpu_addr, in amdgpu_ih_ring_alloc()
47 (void **)&adev->irq.ih.ring); in amdgpu_ih_ring_alloc()
65 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, in amdgpu_ih_ring_init() argument
74 adev->irq.ih.ring_size = ring_size; in amdgpu_ih_ring_init()
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; in amdgpu_ih_ring_init()
76 adev->irq.ih.rptr = 0; in amdgpu_ih_ring_init()
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| D | amdgpu_gart.c | 69 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_init() argument
71 struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page; in amdgpu_gart_dummy_page_init()
73 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
75 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
77 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
78 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in amdgpu_gart_dummy_page_init()
79 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_init()
92 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_fini() argument
94 if (!adev->dummy_page_addr) in amdgpu_gart_dummy_page_fini()
96 pci_unmap_page(adev->pdev, adev->dummy_page_addr, in amdgpu_gart_dummy_page_fini()
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| D | gmc_v9_0.c | 200 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_vm_fault_interrupt_state() argument
219 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
230 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
245 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, in gmc_v9_0_process_interrupt() argument
249 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v9_0_process_interrupt()
256 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_process_interrupt()
264 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v9_0_process_interrupt()
266 dev_err(adev->dev, in gmc_v9_0_process_interrupt()
272 dev_err(adev->dev, " at address 0x%016llx from %d\n", in gmc_v9_0_process_interrupt()
274 if (!amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
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| D | tonga_ih.c | 49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) in tonga_ih_enable_interrupts() argument
65 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) in tonga_ih_disable_interrupts() argument
85 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
86 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
100 static int tonga_ih_irq_init(struct amdgpu_device *adev) in tonga_ih_irq_init() argument
107 tonga_ih_disable_interrupts(adev); in tonga_ih_irq_init()
110 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in tonga_ih_irq_init()
121 if (adev->irq.ih.use_bus_addr) in tonga_ih_irq_init()
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| D | amdgpu_dpm.h | 242 #define amdgpu_dpm_pre_set_power_state(adev) \ argument
243 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
245 #define amdgpu_dpm_set_power_state(adev) \ argument
246 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
248 #define amdgpu_dpm_post_set_power_state(adev) \ argument
249 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
251 #define amdgpu_dpm_display_configuration_changed(adev) \ argument
252 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
254 #define amdgpu_dpm_print_power_state(adev, ps) \ argument
255 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
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| D | amdgpu_irq.c | 81 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_hotplug_work_func() local
83 struct drm_device *dev = adev->ddev; in amdgpu_hotplug_work_func()
105 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_irq_reset_work_func() local
108 if (!amdgpu_sriov_vf(adev)) in amdgpu_irq_reset_work_func()
109 amdgpu_device_gpu_recover(adev, NULL, false); in amdgpu_irq_reset_work_func()
119 void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
125 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
127 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
131 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
138 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
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| D | amdgpu_pm.c | 36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
68 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
69 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
71 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
73 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
74 if (adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
75 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
76 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
119 struct amdgpu_device *adev = ddev->dev_private; in amdgpu_get_dpm_state() local
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| D | gmc_v6_0.c | 40 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
41 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
70 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) in gmc_v6_0_mc_stop() argument
74 gmc_v6_0_wait_for_idle((void *)adev); in gmc_v6_0_mc_stop()
90 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) in gmc_v6_0_mc_resume() argument
104 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) in gmc_v6_0_init_microcode() argument
113 switch (adev->asic_type) { in gmc_v6_0_init_microcode()
140 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
144 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v6_0_init_microcode()
148 dev_err(adev->dev, in gmc_v6_0_init_microcode()
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| D | kv_dpm.c | 47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
48 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
50 static void kv_init_graphics_levels(struct amdgpu_device *adev);
51 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
54 static void kv_enable_new_levels(struct amdgpu_device *adev);
55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
58 static int kv_set_enabled_levels(struct amdgpu_device *adev);
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| D | amdgpu_virt.c | 29 uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) in amdgpu_csa_vaddr() argument
31 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
41 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) in amdgpu_virt_mmio_blocked() argument
49 int amdgpu_allocate_static_csa(struct amdgpu_device *adev) in amdgpu_allocate_static_csa() argument
54 r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE, in amdgpu_allocate_static_csa()
55 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj, in amdgpu_allocate_static_csa()
56 &adev->virt.csa_vmid0_addr, &ptr); in amdgpu_allocate_static_csa()
64 void amdgpu_free_static_csa(struct amdgpu_device *adev) { in amdgpu_free_static_csa() argument
65 amdgpu_bo_free_kernel(&adev->virt.csa_obj, in amdgpu_free_static_csa()
66 &adev->virt.csa_vmid0_addr, in amdgpu_free_static_csa()
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| D | cik.c | 75 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) in cik_pcie_rreg() argument
80 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
84 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
88 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_pcie_wreg() argument
92 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
100 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) in cik_smc_rreg() argument
105 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_rreg()
108 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_rreg()
112 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_smc_wreg() argument
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| D | vega10_ih.c | 36 static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
45 static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) in vega10_ih_enable_interrupts() argument
52 adev->irq.ih.enabled = true; in vega10_ih_enable_interrupts()
62 static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) in vega10_ih_disable_interrupts() argument
72 adev->irq.ih.enabled = false; in vega10_ih_disable_interrupts()
73 adev->irq.ih.rptr = 0; in vega10_ih_disable_interrupts()
87 static int vega10_ih_irq_init(struct amdgpu_device *adev) in vega10_ih_irq_init() argument
96 vega10_ih_disable_interrupts(adev); in vega10_ih_irq_init()
98 adev->nbio_funcs->ih_control(adev); in vega10_ih_irq_init()
102 if (adev->irq.ih.use_bus_addr) { in vega10_ih_irq_init()
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| D | gfx_v9_0.c | 244 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
245 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
246 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
247 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
248 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
250 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
251 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
254 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) in gfx_v9_0_init_golden_registers() argument
256 switch (adev->asic_type) { in gfx_v9_0_init_golden_registers()
258 soc15_program_register_sequence(adev, in gfx_v9_0_init_golden_registers()
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| D | amdgpu_cgs.c | 35 struct amdgpu_device *adev; member
39 struct amdgpu_device *adev = \
40 ((struct amdgpu_cgs_device *)cgs_device)->adev
141 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert()
166 fw_version = adev->sdma.instance[0].fw_version; in amdgpu_get_firmware_version()
169 fw_version = adev->sdma.instance[1].fw_version; in amdgpu_get_firmware_version()
172 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
175 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
178 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
181 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
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| D | amdgpu_bios.c | 89 static bool igp_read_bios_from_vram(struct amdgpu_device *adev) in igp_read_bios_from_vram() argument
95 if (!(adev->flags & AMD_IS_APU)) in igp_read_bios_from_vram()
96 if (amdgpu_device_need_post(adev)) in igp_read_bios_from_vram()
99 adev->bios = NULL; in igp_read_bios_from_vram()
100 vram_base = pci_resource_start(adev->pdev, 0); in igp_read_bios_from_vram()
106 adev->bios = kmalloc(size, GFP_KERNEL); in igp_read_bios_from_vram()
107 if (!adev->bios) { in igp_read_bios_from_vram()
111 adev->bios_size = size; in igp_read_bios_from_vram()
112 memcpy_fromio(adev->bios, bios, size); in igp_read_bios_from_vram()
115 if (!check_atom_bios(adev->bios, size)) { in igp_read_bios_from_vram()
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| D | amdgpu_amdkfd.c | 80 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) in amdgpu_amdkfd_device_probe() argument
87 switch (adev->asic_type) { in amdgpu_amdkfd_device_probe()
106 dev_info(adev->dev, "kfd not supported on this ASIC\n"); in amdgpu_amdkfd_device_probe()
110 adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
111 adev->pdev, kfd2kgd); in amdgpu_amdkfd_device_probe()
127 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, in amdgpu_doorbell_get_kfd_info() argument
136 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { in amdgpu_doorbell_get_kfd_info()
137 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
138 *aperture_size = adev->doorbell.size; in amdgpu_doorbell_get_kfd_info()
139 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); in amdgpu_doorbell_get_kfd_info()
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| D | mxgpu_ai.c | 34 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_ai_mailbox_send_ack() argument
39 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_ai_mailbox_set_valid() argument
53 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_ai_mailbox_peek_msg() argument
60 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_ai_mailbox_rcv_msg() argument
70 xgpu_ai_mailbox_send_ack(adev); in xgpu_ai_mailbox_rcv_msg()
75 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { in xgpu_ai_peek_ack() argument
79 static int xgpu_ai_poll_ack(struct amdgpu_device *adev) in xgpu_ai_poll_ack() argument
98 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_ai_poll_msg() argument
103 r = xgpu_ai_mailbox_rcv_msg(adev, event); in xgpu_ai_poll_msg()
116 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_ai_mailbox_trans_msg() argument
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| D | gmc_v7_0.c | 49 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
50 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
70 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) in gmc_v7_0_init_golden_registers() argument
72 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
74 amdgpu_device_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
77 amdgpu_device_program_register_sequence(adev, in gmc_v7_0_init_golden_registers()
86 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) in gmc_v7_0_mc_stop() argument
90 gmc_v7_0_wait_for_idle((void *)adev); in gmc_v7_0_mc_stop()
105 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) in gmc_v7_0_mc_resume() argument
128 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) in gmc_v7_0_init_microcode() argument
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| D | amdgpu_gfx.c | 41 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) in amdgpu_gfx_scratch_get() argument
45 i = ffs(adev->gfx.scratch.free_mask); in amdgpu_gfx_scratch_get()
46 if (i != 0 && i <= adev->gfx.scratch.num_reg) { in amdgpu_gfx_scratch_get()
48 adev->gfx.scratch.free_mask &= ~(1u << i); in amdgpu_gfx_scratch_get()
49 *reg = adev->gfx.scratch.reg_base + i; in amdgpu_gfx_scratch_get()
63 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) in amdgpu_gfx_scratch_free() argument
65 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
112 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) in amdgpu_gfx_is_multipipe_capable() argument
122 if (adev->asic_type == CHIP_POLARIS11) in amdgpu_gfx_is_multipipe_capable()
125 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_multipipe_capable()
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| D | cik_ih.c | 49 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void cik_ih_enable_interrupts(struct amdgpu_device *adev) in cik_ih_enable_interrupts() argument
67 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
77 static void cik_ih_disable_interrupts(struct amdgpu_device *adev) in cik_ih_disable_interrupts() argument
89 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
104 static int cik_ih_irq_init(struct amdgpu_device *adev) in cik_ih_irq_init() argument
111 cik_ih_disable_interrupts(adev); in cik_ih_irq_init()
114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in cik_ih_irq_init()
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
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| D | amdgpu_acp.c | 97 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_init() local
99 adev->acp.parent = adev->dev; in acp_sw_init()
101 adev->acp.cgs_device = in acp_sw_init()
102 amdgpu_cgs_create_device(adev); in acp_sw_init()
103 if (!adev->acp.cgs_device) in acp_sw_init()
111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_fini() local
113 if (adev->acp.cgs_device) in acp_sw_fini()
114 amdgpu_cgs_destroy_device(adev->acp.cgs_device); in acp_sw_fini()
281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_hw_init() local
284 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); in acp_hw_init()
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| D | gfx_v7_0.c | 56 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
57 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
58 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
887 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
901 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) in gfx_v7_0_init_microcode() argument
909 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
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