Lines Matching refs:adev
71 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
75 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
76 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
78 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
82 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_rreg()
86 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
90 address = adev->nbio_funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
91 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
93 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in soc15_pcie_wreg()
101 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
109 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
112 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
116 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
123 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
126 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
129 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
137 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
140 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
144 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
151 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
157 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
162 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
165 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
169 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
179 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
184 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
187 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
191 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
201 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
203 return adev->nbio_funcs->get_memsize(adev); in soc15_get_config_memsize()
206 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
208 return adev->clock.spll.reference_freq; in soc15_get_xclk()
212 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
224 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) in soc15_vga_set_state() argument
229 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
235 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, in soc15_read_bios_from_rom() argument
246 if (adev->flags & AMD_IS_APU) in soc15_read_bios_from_rom()
292 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
297 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
299 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
304 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc15_read_indexed_register()
305 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
309 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
314 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
317 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
319 return adev->gfx.config.db_debug2; in soc15_get_register_value()
324 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
333 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
337 *value = soc15_get_register_value(adev, in soc15_read_register()
357 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
367 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
382 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
386 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in soc15_asic_reset()
388 dev_info(adev->dev, "GPU reset\n"); in soc15_asic_reset()
391 pci_clear_master(adev->pdev); in soc15_asic_reset()
393 pci_save_state(adev->pdev); in soc15_asic_reset()
395 psp_gpu_reset(adev); in soc15_asic_reset()
397 pci_restore_state(adev->pdev); in soc15_asic_reset()
400 for (i = 0; i < adev->usec_timeout; i++) { in soc15_asic_reset()
401 u32 memsize = adev->nbio_funcs->get_memsize(adev); in soc15_asic_reset()
408 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in soc15_asic_reset()
419 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
432 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
439 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) in soc15_pcie_gen3_enable() argument
441 if (pci_is_root_bus(adev->pdev->bus)) in soc15_pcie_gen3_enable()
447 if (adev->flags & AMD_IS_APU) in soc15_pcie_gen3_enable()
450 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc15_pcie_gen3_enable()
457 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
466 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, in soc15_enable_doorbell_aperture() argument
469 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); in soc15_enable_doorbell_aperture()
470 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); in soc15_enable_doorbell_aperture()
482 int soc15_set_ip_blocks(struct amdgpu_device *adev) in soc15_set_ip_blocks() argument
485 switch (adev->asic_type) { in soc15_set_ip_blocks()
489 vega10_reg_base_init(adev); in soc15_set_ip_blocks()
492 vega20_reg_base_init(adev); in soc15_set_ip_blocks()
498 if (adev->flags & AMD_IS_APU) in soc15_set_ip_blocks()
499 adev->nbio_funcs = &nbio_v7_0_funcs; in soc15_set_ip_blocks()
500 else if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
501 adev->nbio_funcs = &nbio_v7_0_funcs; in soc15_set_ip_blocks()
503 adev->nbio_funcs = &nbio_v6_1_funcs; in soc15_set_ip_blocks()
505 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
506 adev->df_funcs = &df_v3_6_funcs; in soc15_set_ip_blocks()
508 adev->df_funcs = &df_v1_7_funcs; in soc15_set_ip_blocks()
509 adev->nbio_funcs->detect_hw_virt(adev); in soc15_set_ip_blocks()
511 if (amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
512 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_ip_blocks()
514 switch (adev->asic_type) { in soc15_set_ip_blocks()
518 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
519 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
520 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
521 if (adev->asic_type != CHIP_VEGA20) { in soc15_set_ip_blocks()
522 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
523 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
524 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
526 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
527 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
529 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
530 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
534 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
535 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
536 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); in soc15_set_ip_blocks()
537 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); in soc15_set_ip_blocks()
540 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
541 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
542 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
543 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); in soc15_set_ip_blocks()
544 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
545 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
546 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
548 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
549 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
553 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
554 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
555 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); in soc15_set_ip_blocks()
564 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) in soc15_get_rev_id() argument
566 return adev->nbio_funcs->get_rev_id(adev); in soc15_get_rev_id()
569 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in soc15_flush_hdp() argument
571 adev->nbio_funcs->hdp_flush(adev, ring); in soc15_flush_hdp()
574 static void soc15_invalidate_hdp(struct amdgpu_device *adev, in soc15_invalidate_hdp() argument
584 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
610 adev->smc_rreg = NULL; in soc15_common_early_init()
611 adev->smc_wreg = NULL; in soc15_common_early_init()
612 adev->pcie_rreg = &soc15_pcie_rreg; in soc15_common_early_init()
613 adev->pcie_wreg = &soc15_pcie_wreg; in soc15_common_early_init()
614 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
615 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
616 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
617 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
618 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
619 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
620 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
621 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
623 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
625 adev->rev_id = soc15_get_rev_id(adev); in soc15_common_early_init()
626 adev->external_rev_id = 0xFF; in soc15_common_early_init()
627 switch (adev->asic_type) { in soc15_common_early_init()
629 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
648 adev->pg_flags = 0; in soc15_common_early_init()
649 adev->external_rev_id = 0x1; in soc15_common_early_init()
652 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
670 adev->pg_flags = 0; in soc15_common_early_init()
671 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
674 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
692 adev->pg_flags = 0; in soc15_common_early_init()
693 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
696 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
717 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
719 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) in soc15_common_early_init()
720 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | in soc15_common_early_init()
724 adev->external_rev_id = 0x1; in soc15_common_early_init()
731 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
732 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
733 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
741 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
743 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
744 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
751 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
753 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
754 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
766 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
769 soc15_pcie_gen3_enable(adev); in soc15_common_hw_init()
771 soc15_program_aspm(adev); in soc15_common_hw_init()
773 adev->nbio_funcs->init_registers(adev); in soc15_common_hw_init()
775 soc15_enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
785 soc15_enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
786 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
787 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
794 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
796 return soc15_common_hw_fini(adev); in soc15_common_suspend()
801 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
803 return soc15_common_hw_init(adev); in soc15_common_resume()
821 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_hdp_light_sleep() argument
827 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in soc15_update_hdp_light_sleep()
836 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
842 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
865 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
871 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
880 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in soc15_update_rom_medium_grain_clock_gating() argument
887 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in soc15_update_rom_medium_grain_clock_gating()
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
903 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
906 switch (adev->asic_type) { in soc15_common_set_clockgating_state()
910 adev->nbio_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
912 adev->nbio_funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
914 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
916 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
918 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
920 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
922 adev->df_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
926 adev->nbio_funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
928 adev->nbio_funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
930 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
932 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
934 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
936 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
947 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
950 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
953 adev->nbio_funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
975 adev->df_funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()