34 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)  in xgpu_ai_mailbox_send_ack()  argument
39 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)  in xgpu_ai_mailbox_set_valid()  argument
53 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev)  in xgpu_ai_mailbox_peek_msg()  argument
60 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,  in xgpu_ai_mailbox_rcv_msg()  argument
70 	xgpu_ai_mailbox_send_ack(adev);  in xgpu_ai_mailbox_rcv_msg()
75 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {  in xgpu_ai_peek_ack()  argument
79 static int xgpu_ai_poll_ack(struct amdgpu_device *adev)  in xgpu_ai_poll_ack()  argument
98 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)  in xgpu_ai_poll_msg()  argument
103 		r = xgpu_ai_mailbox_rcv_msg(adev, event);  in xgpu_ai_poll_msg()
116 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,  in xgpu_ai_mailbox_trans_msg()  argument
129 		xgpu_ai_mailbox_set_valid(adev, false);  in xgpu_ai_mailbox_trans_msg()
130 		trn = xgpu_ai_peek_ack(adev);  in xgpu_ai_mailbox_trans_msg()
150 	xgpu_ai_mailbox_set_valid(adev, true);  in xgpu_ai_mailbox_trans_msg()
153 	r = xgpu_ai_poll_ack(adev);  in xgpu_ai_mailbox_trans_msg()
157 	xgpu_ai_mailbox_set_valid(adev, false);  in xgpu_ai_mailbox_trans_msg()
160 static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,  in xgpu_ai_send_access_requests()  argument
165 	xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);  in xgpu_ai_send_access_requests()
171 		r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);  in xgpu_ai_send_access_requests()
178 			adev->virt.fw_reserve.checksum_key =  in xgpu_ai_send_access_requests()
187 static int xgpu_ai_request_reset(struct amdgpu_device *adev)  in xgpu_ai_request_reset()  argument
189 	return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);  in xgpu_ai_request_reset()
192 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,  in xgpu_ai_request_full_gpu_access()  argument
198 	return xgpu_ai_send_access_requests(adev, req);  in xgpu_ai_request_full_gpu_access()
201 static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,  in xgpu_ai_release_full_gpu_access()  argument
208 	r = xgpu_ai_send_access_requests(adev, req);  in xgpu_ai_release_full_gpu_access()
213 static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,  in xgpu_ai_mailbox_ack_irq()  argument
221 static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,  in xgpu_ai_set_mailbox_ack_irq()  argument
238 	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);  in xgpu_ai_mailbox_flr_work()  local
250 	locked = mutex_trylock(&adev->lock_reset);  in xgpu_ai_mailbox_flr_work()
252 		adev->in_gpu_reset = 1;  in xgpu_ai_mailbox_flr_work()
255 		if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)  in xgpu_ai_mailbox_flr_work()
264 		adev->in_gpu_reset = 0;  in xgpu_ai_mailbox_flr_work()
265 		mutex_unlock(&adev->lock_reset);  in xgpu_ai_mailbox_flr_work()
270 		amdgpu_device_gpu_recover(adev, NULL, true);  in xgpu_ai_mailbox_flr_work()
273 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,  in xgpu_ai_set_mailbox_rcv_irq()  argument
287 static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,  in xgpu_ai_mailbox_rcv_irq()  argument
291 	enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);  in xgpu_ai_mailbox_rcv_irq()
295 		if (amdgpu_sriov_runtime(adev))  in xgpu_ai_mailbox_rcv_irq()
296 			schedule_work(&adev->virt.flr_work);  in xgpu_ai_mailbox_rcv_irq()
322 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)  in xgpu_ai_mailbox_set_irq_funcs()  argument
324 	adev->virt.ack_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
325 	adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
326 	adev->virt.rcv_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
327 	adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
330 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)  in xgpu_ai_mailbox_add_irq_id()  argument
334 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);  in xgpu_ai_mailbox_add_irq_id()
338 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);  in xgpu_ai_mailbox_add_irq_id()
340 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_add_irq_id()
347 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)  in xgpu_ai_mailbox_get_irq()  argument
351 	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
354 	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_get_irq()
356 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
360 	INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);  in xgpu_ai_mailbox_get_irq()
365 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)  in xgpu_ai_mailbox_put_irq()  argument
367 	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_put_irq()
368 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_put_irq()