Lines Matching refs:adev
56 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
57 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
58 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
887 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
901 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) in gfx_v7_0_init_microcode() argument
909 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
929 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
932 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
937 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
940 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
945 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
948 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
953 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
956 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
960 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_init_microcode()
962 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
965 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
971 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
974 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
979 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
980 adev->gfx.pfp_fw = NULL; in gfx_v7_0_init_microcode()
981 release_firmware(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
982 adev->gfx.me_fw = NULL; in gfx_v7_0_init_microcode()
983 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
984 adev->gfx.ce_fw = NULL; in gfx_v7_0_init_microcode()
985 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
986 adev->gfx.mec_fw = NULL; in gfx_v7_0_init_microcode()
987 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
988 adev->gfx.mec2_fw = NULL; in gfx_v7_0_init_microcode()
989 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
990 adev->gfx.rlc_fw = NULL; in gfx_v7_0_init_microcode()
995 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) in gfx_v7_0_free_microcode() argument
997 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
998 adev->gfx.pfp_fw = NULL; in gfx_v7_0_free_microcode()
999 release_firmware(adev->gfx.me_fw); in gfx_v7_0_free_microcode()
1000 adev->gfx.me_fw = NULL; in gfx_v7_0_free_microcode()
1001 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
1002 adev->gfx.ce_fw = NULL; in gfx_v7_0_free_microcode()
1003 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
1004 adev->gfx.mec_fw = NULL; in gfx_v7_0_free_microcode()
1005 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
1006 adev->gfx.mec2_fw = NULL; in gfx_v7_0_free_microcode()
1007 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
1008 adev->gfx.rlc_fw = NULL; in gfx_v7_0_free_microcode()
1022 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) in gfx_v7_0_tiling_mode_table_init() argument
1025 ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1027 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v7_0_tiling_mode_table_init()
1031 tile = adev->gfx.config.tile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1032 macrotile = adev->gfx.config.macrotile_mode_array; in gfx_v7_0_tiling_mode_table_init()
1034 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1052 switch (adev->asic_type) { in gfx_v7_0_tiling_mode_table_init()
1587 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, in gfx_v7_0_select_se_sh() argument
1620 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) in gfx_v7_0_get_rb_active_bitmap() argument
1630 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()
1631 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1637 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) in gfx_v7_0_raster_config() argument
1639 switch (adev->asic_type) { in gfx_v7_0_raster_config()
1663 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v7_0_raster_config()
1669 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, in gfx_v7_0_write_harvested_raster_configs() argument
1673 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1674 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
1768 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); in gfx_v7_0_write_harvested_raster_configs()
1774 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_write_harvested_raster_configs()
1786 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) in gfx_v7_0_setup_rb() argument
1792 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()
1793 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1796 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1799 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v7_0_setup_rb()
1800 data = gfx_v7_0_get_rb_active_bitmap(adev); in gfx_v7_0_setup_rb()
1801 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1805 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_setup_rb()
1807 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v7_0_setup_rb()
1808 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v7_0_setup_rb()
1810 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()
1811 adev->gfx.config.max_shader_engines, 16); in gfx_v7_0_setup_rb()
1813 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); in gfx_v7_0_setup_rb()
1815 if (!adev->gfx.config.backend_enable_mask || in gfx_v7_0_setup_rb()
1816 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v7_0_setup_rb()
1820 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, in gfx_v7_0_setup_rb()
1821 adev->gfx.config.backend_enable_mask, in gfx_v7_0_setup_rb()
1826 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1827 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1828 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v7_0_setup_rb()
1829 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v7_0_setup_rb()
1831 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v7_0_setup_rb()
1833 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v7_0_setup_rb()
1835 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v7_0_setup_rb()
1839 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_setup_rb()
1840 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
1854 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) in gfx_v7_0_init_compute_vmid() argument
1870 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_init_compute_vmid()
1872 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_init_compute_vmid()
1879 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_init_compute_vmid()
1880 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_init_compute_vmid()
1883 static void gfx_v7_0_config_init(struct amdgpu_device *adev) in gfx_v7_0_config_init() argument
1885 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v7_0_config_init()
1896 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) in gfx_v7_0_gpu_init() argument
1904 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1905 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1906 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_gpu_init()
1908 gfx_v7_0_tiling_mode_table_init(adev); in gfx_v7_0_gpu_init()
1910 gfx_v7_0_setup_rb(adev); in gfx_v7_0_gpu_init()
1911 gfx_v7_0_get_cu_info(adev); in gfx_v7_0_gpu_init()
1912 gfx_v7_0_config_init(adev); in gfx_v7_0_gpu_init()
1919 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_gpu_init()
1924 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_gpu_init()
1944 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_gpu_init()
1945 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { in gfx_v7_0_gpu_init()
1949 sh_mem_base = adev->gmc.shared_aperture_start >> 48; in gfx_v7_0_gpu_init()
1950 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_gpu_init()
1957 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_gpu_init()
1958 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_gpu_init()
1960 gfx_v7_0_init_compute_vmid(adev); in gfx_v7_0_gpu_init()
1989 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_gpu_init()
1990 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
1991 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
1992 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_gpu_init()
2022 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_gpu_init()
2040 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) in gfx_v7_0_scratch_init() argument
2042 adev->gfx.scratch.num_reg = 8; in gfx_v7_0_scratch_init()
2043 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v7_0_scratch_init()
2044 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v7_0_scratch_init()
2060 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ring() local
2066 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v7_0_ring_test_ring()
2075 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ring()
2083 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_ring_test_ring()
2089 if (i < adev->usec_timeout) { in gfx_v7_0_ring_test_ring()
2096 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ring()
2311 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ib() local
2318 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v7_0_ring_test_ib()
2325 r = amdgpu_ib_get(adev, NULL, 256, &ib); in gfx_v7_0_ring_test_ib()
2359 amdgpu_ib_free(adev, &ib, NULL); in gfx_v7_0_ring_test_ib()
2362 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ib()
2397 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_gfx_enable() argument
2405 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_cp_gfx_enable()
2406 adev->gfx.gfx_ring[i].ready = false; in gfx_v7_0_cp_gfx_enable()
2419 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_load_microcode() argument
2427 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2430 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2431 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2432 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2437 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2438 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2439 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2440 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2441 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2442 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2444 gfx_v7_0_cp_gfx_enable(adev, false); in gfx_v7_0_cp_gfx_load_microcode()
2448 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2454 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2458 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2464 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2468 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2474 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2488 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_start() argument
2490 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2496 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2500 gfx_v7_0_cp_gfx_enable(adev, true); in gfx_v7_0_cp_gfx_start()
2502 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); in gfx_v7_0_cp_gfx_start()
2522 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2536 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2537 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2564 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_resume() argument
2573 if (adev->asic_type != CHIP_HAWAII) in gfx_v7_0_cp_gfx_resume()
2586 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2600 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_cp_gfx_resume()
2615 gfx_v7_0_cp_gfx_start(adev); in gfx_v7_0_cp_gfx_resume()
2628 return ring->adev->wb.wb[ring->rptr_offs]; in gfx_v7_0_ring_get_rptr()
2633 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_get_wptr_gfx() local
2640 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_gfx() local
2649 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2654 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_compute() local
2657 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2669 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_compute_enable() argument
2677 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_cp_compute_enable()
2678 adev->gfx.compute_ring[i].ready = false; in gfx_v7_0_cp_compute_enable()
2691 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_load_microcode() argument
2697 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
2700 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2702 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2703 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2706 gfx_v7_0_cp_compute_enable(adev, false); in gfx_v7_0_cp_compute_load_microcode()
2710 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2718 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_cp_compute_load_microcode()
2721 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
2724 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
2726 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
2727 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
2732 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
2752 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_fini() argument
2756 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2757 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
2763 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) in gfx_v7_0_mec_fini() argument
2765 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v7_0_mec_fini()
2768 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) in gfx_v7_0_mec_init() argument
2774 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2777 amdgpu_gfx_compute_queue_acquire(adev); in gfx_v7_0_mec_init()
2780 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
2783 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, in gfx_v7_0_mec_init()
2785 &adev->gfx.mec.hpd_eop_obj, in gfx_v7_0_mec_init()
2786 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v7_0_mec_init()
2789 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); in gfx_v7_0_mec_init()
2790 gfx_v7_0_mec_fini(adev); in gfx_v7_0_mec_init()
2797 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2798 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
2842 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, in gfx_v7_0_compute_pipe_init() argument
2847 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) in gfx_v7_0_compute_pipe_init()
2850 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_compute_pipe_init()
2851 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; in gfx_v7_0_compute_pipe_init()
2853 cik_srbm_select(adev, mec + 1, pipe, 0, 0); in gfx_v7_0_compute_pipe_init()
2868 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_pipe_init()
2869 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_compute_pipe_init()
2872 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) in gfx_v7_0_mqd_deactivate() argument
2879 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_mqd_deactivate()
2885 if (i == adev->usec_timeout) in gfx_v7_0_mqd_deactivate()
2896 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, in gfx_v7_0_mqd_init() argument
2957 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
2962 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_mqd_init()
3016 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) in gfx_v7_0_mqd_commit() argument
3041 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) in gfx_v7_0_compute_queue_init() argument
3046 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_queue_init()
3048 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, in gfx_v7_0_compute_queue_init()
3052 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); in gfx_v7_0_compute_queue_init()
3056 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_compute_queue_init()
3057 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v7_0_compute_queue_init()
3059 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); in gfx_v7_0_compute_queue_init()
3060 gfx_v7_0_mqd_deactivate(adev); in gfx_v7_0_compute_queue_init()
3061 gfx_v7_0_mqd_commit(adev, mqd); in gfx_v7_0_compute_queue_init()
3063 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_queue_init()
3064 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_compute_queue_init()
3080 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_resume() argument
3092 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3093 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3094 gfx_v7_0_compute_pipe_init(adev, i, j); in gfx_v7_0_cp_compute_resume()
3097 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3098 r = gfx_v7_0_compute_queue_init(adev, i); in gfx_v7_0_cp_compute_resume()
3100 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_cp_compute_resume()
3105 gfx_v7_0_cp_compute_enable(adev, true); in gfx_v7_0_cp_compute_resume()
3107 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3108 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3118 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_enable() argument
3120 gfx_v7_0_cp_gfx_enable(adev, enable); in gfx_v7_0_cp_enable()
3121 gfx_v7_0_cp_compute_enable(adev, enable); in gfx_v7_0_cp_enable()
3124 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_load_microcode() argument
3128 r = gfx_v7_0_cp_gfx_load_microcode(adev); in gfx_v7_0_cp_load_microcode()
3131 r = gfx_v7_0_cp_compute_load_microcode(adev); in gfx_v7_0_cp_load_microcode()
3138 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, in gfx_v7_0_enable_gui_idle_interrupt() argument
3152 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_resume() argument
3156 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_cp_resume()
3158 r = gfx_v7_0_cp_load_microcode(adev); in gfx_v7_0_cp_resume()
3162 r = gfx_v7_0_cp_gfx_resume(adev); in gfx_v7_0_cp_resume()
3165 r = gfx_v7_0_cp_compute_resume(adev); in gfx_v7_0_cp_resume()
3169 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_cp_resume()
3271 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) in gfx_v7_0_rlc_fini() argument
3273 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3274 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3275 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); in gfx_v7_0_rlc_fini()
3278 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) in gfx_v7_0_rlc_init() argument
3287 if (adev->flags & AMD_IS_APU) { in gfx_v7_0_rlc_init()
3288 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_rlc_init()
3289 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3290 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3293 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3294 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3298 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3299 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3300 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3302 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3303 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3306 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3310 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, in gfx_v7_0_rlc_init()
3312 &adev->gfx.rlc.save_restore_obj, in gfx_v7_0_rlc_init()
3313 &adev->gfx.rlc.save_restore_gpu_addr, in gfx_v7_0_rlc_init()
3314 (void **)&adev->gfx.rlc.sr_ptr); in gfx_v7_0_rlc_init()
3316 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); in gfx_v7_0_rlc_init()
3317 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3322 dst_ptr = adev->gfx.rlc.sr_ptr; in gfx_v7_0_rlc_init()
3323 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_rlc_init()
3325 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3326 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3331 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); in gfx_v7_0_rlc_init()
3333 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, in gfx_v7_0_rlc_init()
3335 &adev->gfx.rlc.clear_state_obj, in gfx_v7_0_rlc_init()
3336 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_rlc_init()
3337 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_rlc_init()
3339 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); in gfx_v7_0_rlc_init()
3340 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3345 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v7_0_rlc_init()
3346 gfx_v7_0_get_csb_buffer(adev, dst_ptr); in gfx_v7_0_rlc_init()
3347 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3348 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3351 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3353 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in gfx_v7_0_rlc_init()
3355 &adev->gfx.rlc.cp_table_obj, in gfx_v7_0_rlc_init()
3356 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_rlc_init()
3357 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_rlc_init()
3359 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); in gfx_v7_0_rlc_init()
3360 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3364 gfx_v7_0_init_cp_pg_table(adev); in gfx_v7_0_rlc_init()
3366 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3367 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3374 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_lbpw() argument
3386 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) in gfx_v7_0_wait_for_rlc_serdes() argument
3391 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_wait_for_rlc_serdes()
3392 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3393 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3394 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v7_0_wait_for_rlc_serdes()
3395 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3402 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_wait_for_rlc_serdes()
3403 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_wait_for_rlc_serdes()
3409 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3416 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) in gfx_v7_0_update_rlc() argument
3425 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) in gfx_v7_0_halt_rlc() argument
3437 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_halt_rlc()
3443 gfx_v7_0_wait_for_rlc_serdes(adev); in gfx_v7_0_halt_rlc()
3449 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) in gfx_v7_0_enter_rlc_safe_mode() argument
3458 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_enter_rlc_safe_mode()
3464 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_enter_rlc_safe_mode()
3471 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) in gfx_v7_0_exit_rlc_safe_mode() argument
3486 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) in gfx_v7_0_rlc_stop() argument
3490 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_rlc_stop()
3492 gfx_v7_0_wait_for_rlc_serdes(adev); in gfx_v7_0_rlc_stop()
3502 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) in gfx_v7_0_rlc_start() argument
3506 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_rlc_start()
3511 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) in gfx_v7_0_rlc_reset() argument
3532 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) in gfx_v7_0_rlc_resume() argument
3539 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
3542 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
3544 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
3545 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
3548 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_rlc_resume()
3554 gfx_v7_0_rlc_reset(adev); in gfx_v7_0_rlc_resume()
3556 gfx_v7_0_init_pg(adev); in gfx_v7_0_rlc_resume()
3561 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_rlc_resume()
3562 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_rlc_resume()
3566 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_rlc_resume()
3572 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
3577 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
3580 gfx_v7_0_enable_lbpw(adev, false); in gfx_v7_0_rlc_resume()
3582 if (adev->asic_type == CHIP_BONAIRE) in gfx_v7_0_rlc_resume()
3585 gfx_v7_0_rlc_start(adev); in gfx_v7_0_rlc_resume()
3590 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_cgcg() argument
3596 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { in gfx_v7_0_enable_cgcg()
3597 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_enable_cgcg()
3599 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_cgcg()
3601 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_cgcg()
3602 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_cgcg()
3609 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_cgcg()
3611 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_cgcg()
3618 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_enable_cgcg()
3629 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_enable_cgcg()
3633 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_mgcg() argument
3637 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { in gfx_v7_0_enable_mgcg()
3638 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { in gfx_v7_0_enable_mgcg()
3639 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { in gfx_v7_0_enable_mgcg()
3653 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_mgcg()
3655 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
3656 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_mgcg()
3662 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
3664 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_mgcg()
3666 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { in gfx_v7_0_enable_mgcg()
3672 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && in gfx_v7_0_enable_mgcg()
3673 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) in gfx_v7_0_enable_mgcg()
3704 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_mgcg()
3706 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
3707 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_mgcg()
3712 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
3714 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_mgcg()
3718 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, in gfx_v7_0_update_cg() argument
3721 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_update_cg()
3724 gfx_v7_0_enable_mgcg(adev, true); in gfx_v7_0_update_cg()
3725 gfx_v7_0_enable_cgcg(adev, true); in gfx_v7_0_update_cg()
3727 gfx_v7_0_enable_cgcg(adev, false); in gfx_v7_0_update_cg()
3728 gfx_v7_0_enable_mgcg(adev, false); in gfx_v7_0_update_cg()
3730 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_update_cg()
3733 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, in gfx_v7_0_enable_sclk_slowdown_on_pu() argument
3739 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) in gfx_v7_0_enable_sclk_slowdown_on_pu()
3747 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, in gfx_v7_0_enable_sclk_slowdown_on_pd() argument
3753 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) in gfx_v7_0_enable_sclk_slowdown_on_pd()
3761 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_cp_pg() argument
3766 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) in gfx_v7_0_enable_cp_pg()
3774 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_gds_pg() argument
3779 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) in gfx_v7_0_enable_gds_pg()
3787 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) in gfx_v7_0_init_cp_pg_table() argument
3795 if (adev->asic_type == CHIP_KAVERI) in gfx_v7_0_init_cp_pg_table()
3798 if (adev->gfx.rlc.cp_table_ptr == NULL) in gfx_v7_0_init_cp_pg_table()
3802 dst_ptr = adev->gfx.rlc.cp_table_ptr; in gfx_v7_0_init_cp_pg_table()
3806 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_init_cp_pg_table()
3808 (adev->gfx.ce_fw->data + in gfx_v7_0_init_cp_pg_table()
3814 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_init_cp_pg_table()
3816 (adev->gfx.pfp_fw->data + in gfx_v7_0_init_cp_pg_table()
3822 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_init_cp_pg_table()
3824 (adev->gfx.me_fw->data + in gfx_v7_0_init_cp_pg_table()
3830 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_init_cp_pg_table()
3832 (adev->gfx.mec_fw->data + in gfx_v7_0_init_cp_pg_table()
3838 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_init_cp_pg_table()
3840 (adev->gfx.mec2_fw->data + in gfx_v7_0_init_cp_pg_table()
3855 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_cgpg() argument
3860 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { in gfx_v7_0_enable_gfx_cgpg()
3885 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, in gfx_v7_0_set_user_cu_inactive_bitmap() argument
3899 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) in gfx_v7_0_get_cu_active_bitmap() argument
3909 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()
3914 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) in gfx_v7_0_init_ao_cu_mask() argument
3918 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v7_0_init_ao_cu_mask()
3922 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v7_0_init_ao_cu_mask()
3926 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_static_mgpg() argument
3932 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) in gfx_v7_0_enable_gfx_static_mgpg()
3940 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_dynamic_mgpg() argument
3946 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) in gfx_v7_0_enable_gfx_dynamic_mgpg()
3957 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) in gfx_v7_0_init_gfx_cgpg() argument
3962 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3964 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3965 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3966 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3972 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3974 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3975 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3983 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3984 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4006 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_update_gfx_pg() argument
4008 gfx_v7_0_enable_gfx_cgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4009 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4010 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4013 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) in gfx_v7_0_get_csb_size() argument
4019 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
4027 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
4045 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, in gfx_v7_0_get_csb_buffer() argument
4052 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
4064 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4080 switch (adev->asic_type) { in gfx_v7_0_get_csb_buffer()
4111 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) in gfx_v7_0_init_pg() argument
4113 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | in gfx_v7_0_init_pg()
4119 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); in gfx_v7_0_init_pg()
4120 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); in gfx_v7_0_init_pg()
4121 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { in gfx_v7_0_init_pg()
4122 gfx_v7_0_init_gfx_cgpg(adev); in gfx_v7_0_init_pg()
4123 gfx_v7_0_enable_cp_pg(adev, true); in gfx_v7_0_init_pg()
4124 gfx_v7_0_enable_gds_pg(adev, true); in gfx_v7_0_init_pg()
4126 gfx_v7_0_init_ao_cu_mask(adev); in gfx_v7_0_init_pg()
4127 gfx_v7_0_update_gfx_pg(adev, true); in gfx_v7_0_init_pg()
4131 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) in gfx_v7_0_fini_pg() argument
4133 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | in gfx_v7_0_fini_pg()
4139 gfx_v7_0_update_gfx_pg(adev, false); in gfx_v7_0_fini_pg()
4140 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { in gfx_v7_0_fini_pg()
4141 gfx_v7_0_enable_cp_pg(adev, false); in gfx_v7_0_fini_pg()
4142 gfx_v7_0_enable_gds_pg(adev, false); in gfx_v7_0_fini_pg()
4155 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) in gfx_v7_0_get_gpu_clock_counter() argument
4159 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4163 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4215 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4225 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4240 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4244 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4245 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4246 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4247 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4248 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
4249 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v7_0_read_wave_data()
4250 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v7_0_read_wave_data()
4251 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); in gfx_v7_0_read_wave_data()
4252 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v7_0_read_wave_data()
4253 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); in gfx_v7_0_read_wave_data()
4254 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); in gfx_v7_0_read_wave_data()
4255 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v7_0_read_wave_data()
4256 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); in gfx_v7_0_read_wave_data()
4257 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); in gfx_v7_0_read_wave_data()
4258 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); in gfx_v7_0_read_wave_data()
4259 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); in gfx_v7_0_read_wave_data()
4260 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); in gfx_v7_0_read_wave_data()
4261 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v7_0_read_wave_data()
4264 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v7_0_read_wave_sgprs() argument
4269 adev, simd, wave, 0, in gfx_v7_0_read_wave_sgprs()
4273 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, in gfx_v7_0_select_me_pipe_q() argument
4276 cik_srbm_select(adev, me, pipe, q, 0); in gfx_v7_0_select_me_pipe_q()
4294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_early_init() local
4296 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4297 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v7_0_early_init()
4298 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; in gfx_v7_0_early_init()
4299 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4300 gfx_v7_0_set_ring_funcs(adev); in gfx_v7_0_early_init()
4301 gfx_v7_0_set_irq_funcs(adev); in gfx_v7_0_early_init()
4302 gfx_v7_0_set_gds_init(adev); in gfx_v7_0_early_init()
4309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_late_init() local
4312 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4316 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4323 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) in gfx_v7_0_gpu_early_init() argument
4330 switch (adev->asic_type) { in gfx_v7_0_gpu_early_init()
4332 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_early_init()
4333 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4334 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()
4335 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4336 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4337 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4338 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4339 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4340 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4342 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4343 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4344 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4345 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4349 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_early_init()
4350 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()
4351 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()
4352 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4353 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()
4354 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_early_init()
4355 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4356 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_early_init()
4357 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4359 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4360 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4361 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4362 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4366 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4367 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()
4368 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()
4369 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()
4370 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4371 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_early_init()
4372 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4373 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4374 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4385 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_early_init()
4386 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()
4387 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()
4388 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4389 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
4390 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_early_init()
4391 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_early_init()
4392 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_early_init()
4393 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_early_init()
4395 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4396 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4397 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4398 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4404 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4405 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_early_init()
4407 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
4408 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_early_init()
4409 if (adev->flags & AMD_IS_APU) { in gfx_v7_0_gpu_early_init()
4432 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_early_init()
4434 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_early_init()
4437 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_early_init()
4438 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_early_init()
4439 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_early_init()
4442 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_early_init()
4443 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_early_init()
4444 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_early_init()
4448 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_early_init()
4460 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_early_init()
4463 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, in gfx_v7_0_compute_ring_init() argument
4468 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v7_0_compute_ring_init()
4481 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v7_0_compute_ring_init()
4485 r = amdgpu_ring_init(adev, ring, 1024, in gfx_v7_0_compute_ring_init()
4486 &adev->gfx.eop_irq, irq_type); in gfx_v7_0_compute_ring_init()
4497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_sw_init() local
4500 switch (adev->asic_type) { in gfx_v7_0_sw_init()
4502 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4509 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4512 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v7_0_sw_init()
4513 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v7_0_sw_init()
4516 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4521 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, in gfx_v7_0_sw_init()
4522 &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4527 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, in gfx_v7_0_sw_init()
4528 &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4532 gfx_v7_0_scratch_init(adev); in gfx_v7_0_sw_init()
4534 r = gfx_v7_0_init_microcode(adev); in gfx_v7_0_sw_init()
4540 r = gfx_v7_0_rlc_init(adev); in gfx_v7_0_sw_init()
4547 r = gfx_v7_0_mec_init(adev); in gfx_v7_0_sw_init()
4553 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4554 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4557 r = amdgpu_ring_init(adev, ring, 1024, in gfx_v7_0_sw_init()
4558 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); in gfx_v7_0_sw_init()
4565 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4566 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4567 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4568 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) in gfx_v7_0_sw_init()
4571 r = gfx_v7_0_compute_ring_init(adev, in gfx_v7_0_sw_init()
4583 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, in gfx_v7_0_sw_init()
4585 &adev->gds.gds_gfx_bo, NULL, NULL); in gfx_v7_0_sw_init()
4589 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, in gfx_v7_0_sw_init()
4591 &adev->gds.gws_gfx_bo, NULL, NULL); in gfx_v7_0_sw_init()
4595 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, in gfx_v7_0_sw_init()
4597 &adev->gds.oa_gfx_bo, NULL, NULL); in gfx_v7_0_sw_init()
4601 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4603 gfx_v7_0_gpu_early_init(adev); in gfx_v7_0_sw_init()
4611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_sw_fini() local
4613 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); in gfx_v7_0_sw_fini()
4614 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); in gfx_v7_0_sw_fini()
4615 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); in gfx_v7_0_sw_fini()
4617 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4618 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4619 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4620 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4622 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_sw_fini()
4623 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_sw_fini()
4624 gfx_v7_0_mec_fini(adev); in gfx_v7_0_sw_fini()
4625 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4626 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4627 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4628 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4629 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4630 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4631 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4633 gfx_v7_0_free_microcode(adev); in gfx_v7_0_sw_fini()
4641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_hw_init() local
4643 gfx_v7_0_gpu_init(adev); in gfx_v7_0_hw_init()
4646 r = gfx_v7_0_rlc_resume(adev); in gfx_v7_0_hw_init()
4650 r = gfx_v7_0_cp_resume(adev); in gfx_v7_0_hw_init()
4659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_hw_fini() local
4661 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4662 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4663 gfx_v7_0_cp_enable(adev, false); in gfx_v7_0_hw_fini()
4664 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_hw_fini()
4665 gfx_v7_0_fini_pg(adev); in gfx_v7_0_hw_fini()
4672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_suspend() local
4674 return gfx_v7_0_hw_fini(adev); in gfx_v7_0_suspend()
4679 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_resume() local
4681 return gfx_v7_0_hw_init(adev); in gfx_v7_0_resume()
4686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_is_idle() local
4698 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_wait_for_idle() local
4700 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_wait_for_idle()
4715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_soft_reset() local
4745 gfx_v7_0_fini_pg(adev); in gfx_v7_0_soft_reset()
4746 gfx_v7_0_update_cg(adev, false); in gfx_v7_0_soft_reset()
4749 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_soft_reset()
4760 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4774 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4790 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_gfx_eop_interrupt_state() argument
4811 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_compute_eop_interrupt_state() argument
4862 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, in gfx_v7_0_set_priv_reg_fault_state() argument
4887 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, in gfx_v7_0_set_priv_inst_fault_state() argument
4912 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_eop_interrupt_state() argument
4919 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); in gfx_v7_0_set_eop_interrupt_state()
4922 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4925 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); in gfx_v7_0_set_eop_interrupt_state()
4928 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); in gfx_v7_0_set_eop_interrupt_state()
4931 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); in gfx_v7_0_set_eop_interrupt_state()
4934 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4937 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); in gfx_v7_0_set_eop_interrupt_state()
4940 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); in gfx_v7_0_set_eop_interrupt_state()
4943 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); in gfx_v7_0_set_eop_interrupt_state()
4951 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, in gfx_v7_0_eop_irq() argument
4964 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4968 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4969 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
4978 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, in gfx_v7_0_priv_reg_irq() argument
4983 schedule_work(&adev->reset_work); in gfx_v7_0_priv_reg_irq()
4987 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, in gfx_v7_0_priv_inst_irq() argument
4993 schedule_work(&adev->reset_work); in gfx_v7_0_priv_inst_irq()
5001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_set_clockgating_state() local
5006 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_set_clockgating_state()
5009 gfx_v7_0_enable_mgcg(adev, true); in gfx_v7_0_set_clockgating_state()
5010 gfx_v7_0_enable_cgcg(adev, true); in gfx_v7_0_set_clockgating_state()
5012 gfx_v7_0_enable_cgcg(adev, false); in gfx_v7_0_set_clockgating_state()
5013 gfx_v7_0_enable_mgcg(adev, false); in gfx_v7_0_set_clockgating_state()
5015 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_set_clockgating_state()
5024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_set_powergating_state() local
5029 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | in gfx_v7_0_set_powergating_state()
5035 gfx_v7_0_update_gfx_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5036 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { in gfx_v7_0_set_powergating_state()
5037 gfx_v7_0_enable_cp_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5038 gfx_v7_0_enable_gds_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5122 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) in gfx_v7_0_set_ring_funcs() argument
5126 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5127 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5128 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5129 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5147 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) in gfx_v7_0_set_irq_funcs() argument
5149 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5150 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5152 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5153 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5155 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5156 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5159 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) in gfx_v7_0_set_gds_init() argument
5162 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5163 adev->gds.gws.total_size = 64; in gfx_v7_0_set_gds_init()
5164 adev->gds.oa.total_size = 16; in gfx_v7_0_set_gds_init()
5166 if (adev->gds.mem.total_size == 64 * 1024) { in gfx_v7_0_set_gds_init()
5167 adev->gds.mem.gfx_partition_size = 4096; in gfx_v7_0_set_gds_init()
5168 adev->gds.mem.cs_partition_size = 4096; in gfx_v7_0_set_gds_init()
5170 adev->gds.gws.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5171 adev->gds.gws.cs_partition_size = 4; in gfx_v7_0_set_gds_init()
5173 adev->gds.oa.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5174 adev->gds.oa.cs_partition_size = 1; in gfx_v7_0_set_gds_init()
5176 adev->gds.mem.gfx_partition_size = 1024; in gfx_v7_0_set_gds_init()
5177 adev->gds.mem.cs_partition_size = 1024; in gfx_v7_0_set_gds_init()
5179 adev->gds.gws.gfx_partition_size = 16; in gfx_v7_0_set_gds_init()
5180 adev->gds.gws.cs_partition_size = 16; in gfx_v7_0_set_gds_init()
5182 adev->gds.oa.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5183 adev->gds.oa.cs_partition_size = 4; in gfx_v7_0_set_gds_init()
5188 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) in gfx_v7_0_get_cu_info() argument
5192 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v7_0_get_cu_info()
5196 if (adev->flags & AMD_IS_APU) in gfx_v7_0_get_cu_info()
5199 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()
5205 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_get_cu_info()
5206 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5207 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5211 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); in gfx_v7_0_get_cu_info()
5214 adev, disable_masks[i * 2 + j]); in gfx_v7_0_get_cu_info()
5215 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); in gfx_v7_0_get_cu_info()
5218 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()
5232 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in gfx_v7_0_get_cu_info()
5233 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_get_cu_info()