75 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)  in cik_pcie_rreg()  argument
80 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in cik_pcie_rreg()
84 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in cik_pcie_rreg()
88 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_pcie_wreg()  argument
92 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in cik_pcie_wreg()
97 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in cik_pcie_wreg()
100 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)  in cik_smc_rreg()  argument
105 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_smc_rreg()
108 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_smc_rreg()
112 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_smc_wreg()  argument
116 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_smc_wreg()
119 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_smc_wreg()
122 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)  in cik_uvd_ctx_rreg()  argument
127 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_rreg()
130 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_rreg()
134 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_uvd_ctx_wreg()  argument
138 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_wreg()
141 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in cik_uvd_ctx_wreg()
144 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)  in cik_didt_rreg()  argument
149 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in cik_didt_rreg()
152 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in cik_didt_rreg()
156 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cik_didt_wreg()  argument
160 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in cik_didt_wreg()
163 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in cik_didt_wreg()
750 static void cik_init_golden_registers(struct amdgpu_device *adev)  in cik_init_golden_registers()  argument
753 	mutex_lock(&adev->grbm_idx_mutex);  in cik_init_golden_registers()
755 	switch (adev->asic_type) {  in cik_init_golden_registers()
757 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
760 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
763 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
766 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
771 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
774 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
777 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
780 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
785 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
788 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
791 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
794 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
799 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
802 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
805 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
808 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
813 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
816 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
819 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
822 		amdgpu_device_program_register_sequence(adev,  in cik_init_golden_registers()
829 	mutex_unlock(&adev->grbm_idx_mutex);  in cik_init_golden_registers()
840 static u32 cik_get_xclk(struct amdgpu_device *adev)  in cik_get_xclk()  argument
842 	u32 reference_clock = adev->clock.spll.reference_freq;  in cik_get_xclk()
844 	if (adev->flags & AMD_IS_APU) {  in cik_get_xclk()
867 void cik_srbm_select(struct amdgpu_device *adev,  in cik_srbm_select()  argument
878 static void cik_vga_set_state(struct amdgpu_device *adev, bool state)  in cik_vga_set_state()  argument
890 static bool cik_read_disabled_bios(struct amdgpu_device *adev)  in cik_read_disabled_bios()  argument
900 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
909 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
922 	r = amdgpu_read_bios(adev);  in cik_read_disabled_bios()
926 	if (adev->mode_info.num_crtc) {  in cik_read_disabled_bios()
935 static bool cik_read_bios_from_rom(struct amdgpu_device *adev,  in cik_read_bios_from_rom()  argument
947 	if (adev->flags & AMD_IS_APU)  in cik_read_bios_from_rom()
953 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cik_read_bios_from_rom()
961 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cik_read_bios_from_rom()
1026 static uint32_t cik_get_register_value(struct amdgpu_device *adev,  in cik_get_register_value()  argument
1037 			return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;  in cik_get_register_value()
1039 			return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;  in cik_get_register_value()
1041 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;  in cik_get_register_value()
1043 			return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;  in cik_get_register_value()
1046 		mutex_lock(&adev->grbm_idx_mutex);  in cik_get_register_value()
1048 			amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);  in cik_get_register_value()
1053 			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);  in cik_get_register_value()
1054 		mutex_unlock(&adev->grbm_idx_mutex);  in cik_get_register_value()
1061 			return adev->gfx.config.gb_addr_config;  in cik_get_register_value()
1063 			return adev->gfx.config.mc_arb_ramcfg;  in cik_get_register_value()
1097 			return adev->gfx.config.tile_mode_array[idx];  in cik_get_register_value()
1115 			return adev->gfx.config.macrotile_mode_array[idx];  in cik_get_register_value()
1122 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,  in cik_read_register()  argument
1134 		*value = cik_get_register_value(adev, indexed, se_num, sh_num,  in cik_read_register()
1147 static void kv_save_regs_for_reset(struct amdgpu_device *adev,  in kv_save_regs_for_reset()  argument
1161 static void kv_restore_regs_for_reset(struct amdgpu_device *adev,  in kv_restore_regs_for_reset()  argument
1234 static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)  in cik_gpu_pci_config_reset()  argument
1240 	dev_info(adev->dev, "GPU pci config reset\n");  in cik_gpu_pci_config_reset()
1242 	if (adev->flags & AMD_IS_APU)  in cik_gpu_pci_config_reset()
1243 		kv_save_regs_for_reset(adev, &kv_save);  in cik_gpu_pci_config_reset()
1246 	pci_clear_master(adev->pdev);  in cik_gpu_pci_config_reset()
1248 	amdgpu_device_pci_config_reset(adev);  in cik_gpu_pci_config_reset()
1253 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_gpu_pci_config_reset()
1256 			pci_set_master(adev->pdev);  in cik_gpu_pci_config_reset()
1257 			adev->has_hw_reset = true;  in cik_gpu_pci_config_reset()
1265 	if (adev->flags & AMD_IS_APU)  in cik_gpu_pci_config_reset()
1266 		kv_restore_regs_for_reset(adev, &kv_save);  in cik_gpu_pci_config_reset()
1280 static int cik_asic_reset(struct amdgpu_device *adev)  in cik_asic_reset()  argument
1284 	amdgpu_atombios_scratch_regs_engine_hung(adev, true);  in cik_asic_reset()
1286 	r = cik_gpu_pci_config_reset(adev);  in cik_asic_reset()
1288 	amdgpu_atombios_scratch_regs_engine_hung(adev, false);  in cik_asic_reset()
1293 static u32 cik_get_config_memsize(struct amdgpu_device *adev)  in cik_get_config_memsize()  argument
1298 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,  in cik_set_uvd_clock()  argument
1305 	r = amdgpu_atombios_get_clock_dividers(adev,  in cik_set_uvd_clock()
1328 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in cik_set_uvd_clocks()  argument
1332 	r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);  in cik_set_uvd_clocks()
1336 	r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);  in cik_set_uvd_clocks()
1340 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)  in cik_set_vce_clocks()  argument
1346 	r = amdgpu_atombios_get_clock_dividers(adev,  in cik_set_vce_clocks()
1377 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)  in cik_pcie_gen3_enable()  argument
1379 	struct pci_dev *root = adev->pdev->bus->self;  in cik_pcie_gen3_enable()
1385 	if (pci_is_root_bus(adev->pdev->bus))  in cik_pcie_gen3_enable()
1391 	if (adev->flags & AMD_IS_APU)  in cik_pcie_gen3_enable()
1394 	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |  in cik_pcie_gen3_enable()
1401 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in cik_pcie_gen3_enable()
1407 	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {  in cik_pcie_gen3_enable()
1419 	gpu_pos = pci_pcie_cap(adev->pdev);  in cik_pcie_gen3_enable()
1423 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {  in cik_pcie_gen3_enable()
1431 			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);  in cik_pcie_gen3_enable()
1437 			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);  in cik_pcie_gen3_enable()
1461 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);  in cik_pcie_gen3_enable()
1466 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);  in cik_pcie_gen3_enable()
1469 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);  in cik_pcie_gen3_enable()
1487 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);  in cik_pcie_gen3_enable()
1490 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);  in cik_pcie_gen3_enable()
1498 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);  in cik_pcie_gen3_enable()
1501 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);  in cik_pcie_gen3_enable()
1516 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);  in cik_pcie_gen3_enable()
1518 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)  in cik_pcie_gen3_enable()
1520 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)  in cik_pcie_gen3_enable()
1524 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);  in cik_pcie_gen3_enable()
1530 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_pcie_gen3_enable()
1538 static void cik_program_aspm(struct amdgpu_device *adev)  in cik_program_aspm()  argument
1547 	if (pci_is_root_bus(adev->pdev->bus))  in cik_program_aspm()
1551 	if (adev->flags & AMD_IS_APU)  in cik_program_aspm()
1626 				struct pci_dev *root = adev->pdev->bus->self;  in cik_program_aspm()
1705 static uint32_t cik_get_rev_id(struct amdgpu_device *adev)  in cik_get_rev_id()  argument
1711 static void cik_detect_hw_virtualization(struct amdgpu_device *adev)  in cik_detect_hw_virtualization()  argument
1714 		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in cik_detect_hw_virtualization()
1717 static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)  in cik_flush_hdp()  argument
1727 static void cik_invalidate_hdp(struct amdgpu_device *adev,  in cik_invalidate_hdp()  argument
1738 static bool cik_need_full_reset(struct amdgpu_device *adev)  in cik_need_full_reset()  argument
1762 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_early_init()  local
1764 	adev->smc_rreg = &cik_smc_rreg;  in cik_common_early_init()
1765 	adev->smc_wreg = &cik_smc_wreg;  in cik_common_early_init()
1766 	adev->pcie_rreg = &cik_pcie_rreg;  in cik_common_early_init()
1767 	adev->pcie_wreg = &cik_pcie_wreg;  in cik_common_early_init()
1768 	adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;  in cik_common_early_init()
1769 	adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;  in cik_common_early_init()
1770 	adev->didt_rreg = &cik_didt_rreg;  in cik_common_early_init()
1771 	adev->didt_wreg = &cik_didt_wreg;  in cik_common_early_init()
1773 	adev->asic_funcs = &cik_asic_funcs;  in cik_common_early_init()
1775 	adev->rev_id = cik_get_rev_id(adev);  in cik_common_early_init()
1776 	adev->external_rev_id = 0xFF;  in cik_common_early_init()
1777 	switch (adev->asic_type) {  in cik_common_early_init()
1779 		adev->cg_flags =  in cik_common_early_init()
1796 		adev->pg_flags = 0;  in cik_common_early_init()
1797 		adev->external_rev_id = adev->rev_id + 0x14;  in cik_common_early_init()
1800 		adev->cg_flags =  in cik_common_early_init()
1816 		adev->pg_flags = 0;  in cik_common_early_init()
1817 		adev->external_rev_id = 0x28;  in cik_common_early_init()
1820 		adev->cg_flags =  in cik_common_early_init()
1835 		adev->pg_flags =  in cik_common_early_init()
1847 		if (adev->pdev->device == 0x1312 ||  in cik_common_early_init()
1848 			adev->pdev->device == 0x1316 ||  in cik_common_early_init()
1849 			adev->pdev->device == 0x1317)  in cik_common_early_init()
1850 			adev->external_rev_id = 0x41;  in cik_common_early_init()
1852 			adev->external_rev_id = 0x1;  in cik_common_early_init()
1856 		adev->cg_flags =  in cik_common_early_init()
1871 		adev->pg_flags =  in cik_common_early_init()
1881 		if (adev->asic_type == CHIP_KABINI) {  in cik_common_early_init()
1882 			if (adev->rev_id == 0)  in cik_common_early_init()
1883 				adev->external_rev_id = 0x81;  in cik_common_early_init()
1884 			else if (adev->rev_id == 1)  in cik_common_early_init()
1885 				adev->external_rev_id = 0x82;  in cik_common_early_init()
1886 			else if (adev->rev_id == 2)  in cik_common_early_init()
1887 				adev->external_rev_id = 0x85;  in cik_common_early_init()
1889 			adev->external_rev_id = adev->rev_id + 0xa1;  in cik_common_early_init()
1911 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_hw_init()  local
1914 	cik_init_golden_registers(adev);  in cik_common_hw_init()
1916 	cik_pcie_gen3_enable(adev);  in cik_common_hw_init()
1918 	cik_program_aspm(adev);  in cik_common_hw_init()
1930 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_suspend()  local
1932 	return cik_common_hw_fini(adev);  in cik_common_suspend()
1937 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_common_resume()  local
1939 	return cik_common_hw_init(adev);  in cik_common_resume()
1996 int cik_set_ip_blocks(struct amdgpu_device *adev)  in cik_set_ip_blocks()  argument
1998 	cik_detect_hw_virtualization(adev);  in cik_set_ip_blocks()
2000 	switch (adev->asic_type) {  in cik_set_ip_blocks()
2002 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2003 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2004 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2006 			amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in cik_set_ip_blocks()
2008 			amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);  in cik_set_ip_blocks()
2009 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2010 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2012 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2013 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2016 			amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);  in cik_set_ip_blocks()
2017 		amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);  in cik_set_ip_blocks()
2018 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2019 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2020 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2023 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2024 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2025 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2027 			amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);  in cik_set_ip_blocks()
2029 			amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);  in cik_set_ip_blocks()
2030 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2031 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2033 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2034 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2037 			amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);  in cik_set_ip_blocks()
2038 		amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);  in cik_set_ip_blocks()
2039 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2040 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2041 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2044 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2045 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2046 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2047 		amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);  in cik_set_ip_blocks()
2048 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2049 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2051 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2052 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2055 			amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);  in cik_set_ip_blocks()
2056 		amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);  in cik_set_ip_blocks()
2057 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2058 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2059 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()
2063 		amdgpu_device_ip_block_add(adev, &cik_common_ip_block);  in cik_set_ip_blocks()
2064 		amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);  in cik_set_ip_blocks()
2065 		amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);  in cik_set_ip_blocks()
2066 		amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);  in cik_set_ip_blocks()
2067 		if (adev->enable_virtual_display)  in cik_set_ip_blocks()
2068 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);  in cik_set_ip_blocks()
2070 		else if (amdgpu_device_has_dc_support(adev))  in cik_set_ip_blocks()
2071 			amdgpu_device_ip_block_add(adev, &dm_ip_block);  in cik_set_ip_blocks()
2074 			amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);  in cik_set_ip_blocks()
2075 		amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);  in cik_set_ip_blocks()
2076 		amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);  in cik_set_ip_blocks()
2077 		amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);  in cik_set_ip_blocks()
2078 		amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);  in cik_set_ip_blocks()