Lines Matching refs:adev
47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
48 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
50 static void kv_init_graphics_levels(struct amdgpu_device *adev);
51 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
54 static void kv_enable_new_levels(struct amdgpu_device *adev);
55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
58 static int kv_set_enabled_levels(struct amdgpu_device *adev);
59 static int kv_force_dpm_highest(struct amdgpu_device *adev);
60 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
61 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
64 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
66 static int kv_init_fps_limits(struct amdgpu_device *adev);
68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
72 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, in kv_convert_vid2_to_vid7() argument
77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
94 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, in kv_convert_vid7_to_vid2() argument
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
118 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) in sumo_take_smu_control() argument
137 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, in sumo_construct_sclk_voltage_mapping_table() argument
159 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, in sumo_construct_vid_mapping_table() argument
378 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) in kv_get_pi() argument
380 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
386 static void kv_program_local_cac_table(struct amdgpu_device *adev,
411 static int kv_program_pt_config_registers(struct amdgpu_device *adev, in kv_program_pt_config_registers() argument
460 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) in kv_do_enable_didt() argument
462 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt()
502 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) in kv_enable_didt() argument
504 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt()
511 adev->gfx.rlc.funcs->enter_safe_mode(adev); in kv_enable_didt()
514 ret = kv_program_pt_config_registers(adev, didt_config_kv); in kv_enable_didt()
516 adev->gfx.rlc.funcs->exit_safe_mode(adev); in kv_enable_didt()
521 kv_do_enable_didt(adev, enable); in kv_enable_didt()
523 adev->gfx.rlc.funcs->exit_safe_mode(adev); in kv_enable_didt()
530 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
532 struct kv_power_info *pi = kv_get_pi(adev);
537 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
541 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
545 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
549 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
553 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
557 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
562 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) in kv_enable_smc_cac() argument
564 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac()
569 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); in kv_enable_smc_cac()
575 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); in kv_enable_smc_cac()
583 static int kv_process_firmware_header(struct amdgpu_device *adev) in kv_process_firmware_header() argument
585 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header()
589 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
596 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
606 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) in kv_enable_dpm_voltage_scaling() argument
608 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling()
613 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_dpm_voltage_scaling()
622 static int kv_set_dpm_interval(struct amdgpu_device *adev) in kv_set_dpm_interval() argument
624 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval()
629 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_interval()
638 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) in kv_set_dpm_boot_state() argument
640 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state()
643 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_boot_state()
652 static void kv_program_vc(struct amdgpu_device *adev) in kv_program_vc() argument
657 static void kv_clear_vc(struct amdgpu_device *adev) in kv_clear_vc() argument
662 static int kv_set_divider_value(struct amdgpu_device *adev, in kv_set_divider_value() argument
665 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value()
669 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_set_divider_value()
680 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_8bit_index_to_voltage() argument
686 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_2bit_index_to_voltage() argument
689 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage()
690 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, in kv_convert_2bit_index_to_voltage()
694 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); in kv_convert_2bit_index_to_voltage()
698 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) in kv_set_vid() argument
700 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid()
704 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); in kv_set_vid()
709 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) in kv_set_at() argument
711 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at()
718 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, in kv_dpm_power_level_enable() argument
721 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable()
726 static void kv_start_dpm(struct amdgpu_device *adev) in kv_start_dpm() argument
733 amdgpu_kv_smc_dpm_enable(adev, true); in kv_start_dpm()
736 static void kv_stop_dpm(struct amdgpu_device *adev) in kv_stop_dpm() argument
738 amdgpu_kv_smc_dpm_enable(adev, false); in kv_stop_dpm()
741 static void kv_start_am(struct amdgpu_device *adev) in kv_start_am() argument
752 static void kv_reset_am(struct amdgpu_device *adev) in kv_reset_am() argument
762 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) in kv_freeze_sclk_dpm() argument
764 return amdgpu_kv_notify_message_to_smu(adev, freeze ? in kv_freeze_sclk_dpm()
768 static int kv_force_lowest_valid(struct amdgpu_device *adev) in kv_force_lowest_valid() argument
770 return kv_force_dpm_lowest(adev); in kv_force_lowest_valid()
773 static int kv_unforce_levels(struct amdgpu_device *adev) in kv_unforce_levels() argument
775 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
776 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); in kv_unforce_levels()
778 return kv_set_enabled_levels(adev); in kv_unforce_levels()
781 static int kv_update_sclk_t(struct amdgpu_device *adev) in kv_update_sclk_t() argument
783 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t()
790 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_sclk_t()
799 static int kv_program_bootup_state(struct amdgpu_device *adev) in kv_program_bootup_state() argument
801 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state()
804 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
813 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
827 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
832 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) in kv_enable_auto_thermal_throttling() argument
834 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling()
839 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_auto_thermal_throttling()
848 static int kv_upload_dpm_settings(struct amdgpu_device *adev) in kv_upload_dpm_settings() argument
850 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings()
853 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
863 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
877 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) in kv_get_clk_bypass() argument
879 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass()
902 static int kv_populate_uvd_table(struct amdgpu_device *adev) in kv_populate_uvd_table() argument
904 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table()
906 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
925 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
927 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); in kv_populate_uvd_table()
929 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
935 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
944 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
954 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
962 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
973 static int kv_populate_vce_table(struct amdgpu_device *adev) in kv_populate_vce_table() argument
975 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table()
979 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
995 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); in kv_populate_vce_table()
997 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_vce_table()
1006 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1017 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1026 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1036 static int kv_populate_samu_table(struct amdgpu_device *adev) in kv_populate_samu_table() argument
1038 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table()
1040 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1058 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); in kv_populate_samu_table()
1060 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_samu_table()
1069 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1080 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1089 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1102 static int kv_populate_acp_table(struct amdgpu_device *adev) in kv_populate_acp_table() argument
1104 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table()
1106 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1119 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_acp_table()
1128 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1139 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1148 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1160 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) in kv_calculate_dfs_bypass_settings() argument
1162 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings()
1165 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1210 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) in kv_enable_ulv() argument
1212 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_ulv()
1216 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) in kv_reset_acp_boot_level() argument
1218 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level()
1223 static void kv_update_current_ps(struct amdgpu_device *adev, in kv_update_current_ps() argument
1227 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps()
1232 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1235 static void kv_update_requested_ps(struct amdgpu_device *adev, in kv_update_requested_ps() argument
1239 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps()
1244 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_enable_bapm() local
1250 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm()
1254 ret = amdgpu_kv_smc_bapm_enable(adev, enable); in kv_dpm_enable_bapm()
1260 static int kv_dpm_enable(struct amdgpu_device *adev) in kv_dpm_enable() argument
1262 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable()
1265 ret = kv_process_firmware_header(adev); in kv_dpm_enable()
1270 kv_init_fps_limits(adev); in kv_dpm_enable()
1271 kv_init_graphics_levels(adev); in kv_dpm_enable()
1272 ret = kv_program_bootup_state(adev); in kv_dpm_enable()
1277 kv_calculate_dfs_bypass_settings(adev); in kv_dpm_enable()
1278 ret = kv_upload_dpm_settings(adev); in kv_dpm_enable()
1283 ret = kv_populate_uvd_table(adev); in kv_dpm_enable()
1288 ret = kv_populate_vce_table(adev); in kv_dpm_enable()
1293 ret = kv_populate_samu_table(adev); in kv_dpm_enable()
1298 ret = kv_populate_acp_table(adev); in kv_dpm_enable()
1303 kv_program_vc(adev); in kv_dpm_enable()
1305 kv_initialize_hardware_cac_manager(adev); in kv_dpm_enable()
1307 kv_start_am(adev); in kv_dpm_enable()
1309 ret = kv_enable_auto_thermal_throttling(adev); in kv_dpm_enable()
1315 ret = kv_enable_dpm_voltage_scaling(adev); in kv_dpm_enable()
1320 ret = kv_set_dpm_interval(adev); in kv_dpm_enable()
1325 ret = kv_set_dpm_boot_state(adev); in kv_dpm_enable()
1330 ret = kv_enable_ulv(adev, true); in kv_dpm_enable()
1335 kv_start_dpm(adev); in kv_dpm_enable()
1336 ret = kv_enable_didt(adev, true); in kv_dpm_enable()
1341 ret = kv_enable_smc_cac(adev, true); in kv_dpm_enable()
1347 kv_reset_acp_boot_level(adev); in kv_dpm_enable()
1349 ret = amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_enable()
1355 if (adev->irq.installed && in kv_dpm_enable()
1356 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { in kv_dpm_enable()
1357 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); in kv_dpm_enable()
1362 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1364 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1371 static void kv_dpm_disable(struct amdgpu_device *adev) in kv_dpm_disable() argument
1373 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable()
1375 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1377 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1380 amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_disable()
1382 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1383 kv_enable_nb_dpm(adev, false); in kv_dpm_disable()
1386 kv_dpm_powergate_acp(adev, false); in kv_dpm_disable()
1387 kv_dpm_powergate_samu(adev, false); in kv_dpm_disable()
1389 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_disable()
1391 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_disable()
1393 kv_enable_smc_cac(adev, false); in kv_dpm_disable()
1394 kv_enable_didt(adev, false); in kv_dpm_disable()
1395 kv_clear_vc(adev); in kv_dpm_disable()
1396 kv_stop_dpm(adev); in kv_dpm_disable()
1397 kv_enable_ulv(adev, false); in kv_dpm_disable()
1398 kv_reset_am(adev); in kv_dpm_disable()
1400 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1404 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1407 struct kv_power_info *pi = kv_get_pi(adev);
1409 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1413 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1416 struct kv_power_info *pi = kv_get_pi(adev);
1418 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1423 static void kv_init_sclk_t(struct amdgpu_device *adev) in kv_init_sclk_t() argument
1425 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t()
1430 static int kv_init_fps_limits(struct amdgpu_device *adev) in kv_init_fps_limits() argument
1432 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits()
1440 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1449 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1459 static void kv_init_powergate_state(struct amdgpu_device *adev) in kv_init_powergate_state() argument
1461 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state()
1470 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_uvd_dpm() argument
1472 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_uvd_dpm()
1476 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_vce_dpm() argument
1478 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_vce_dpm()
1482 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_samu_dpm() argument
1484 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_samu_dpm()
1488 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_acp_dpm() argument
1490 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_acp_dpm()
1494 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in kv_update_uvd_dpm() argument
1496 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm()
1498 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1514 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_uvd_dpm()
1522 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_uvd_dpm()
1527 return kv_enable_uvd_dpm(adev, !gate); in kv_update_uvd_dpm()
1530 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) in kv_get_vce_boot_level() argument
1534 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1544 static int kv_update_vce_dpm(struct amdgpu_device *adev, in kv_update_vce_dpm() argument
1548 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm()
1550 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1557 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1559 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_vce_dpm()
1569 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_vce_dpm()
1572 kv_enable_vce_dpm(adev, true); in kv_update_vce_dpm()
1574 kv_enable_vce_dpm(adev, false); in kv_update_vce_dpm()
1580 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) in kv_update_samu_dpm() argument
1582 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm()
1584 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1593 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_samu_dpm()
1603 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_samu_dpm()
1608 return kv_enable_samu_dpm(adev, !gate); in kv_update_samu_dpm()
1611 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) in kv_get_acp_boot_level() argument
1615 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_get_acp_boot_level()
1628 static void kv_update_acp_boot_level(struct amdgpu_device *adev) in kv_update_acp_boot_level() argument
1630 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level()
1634 acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_boot_level()
1637 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_boot_level()
1644 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) in kv_update_acp_dpm() argument
1646 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm()
1648 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1655 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1657 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_acp_dpm()
1667 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_dpm()
1672 return kv_enable_acp_dpm(adev, !gate); in kv_update_acp_dpm()
1677 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_uvd() local
1678 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd()
1685 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1687 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1690 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); in kv_dpm_powergate_uvd()
1694 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_powergate_uvd()
1696 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1698 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1705 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_powergate_vce() local
1706 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce()
1713 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1715 kv_enable_vce_dpm(adev, false); in kv_dpm_powergate_vce()
1717 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); in kv_dpm_powergate_vce()
1720 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_powergate_vce()
1721 kv_enable_vce_dpm(adev, true); in kv_dpm_powergate_vce()
1723 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1729 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_samu() argument
1731 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu()
1739 kv_update_samu_dpm(adev, true); in kv_dpm_powergate_samu()
1741 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); in kv_dpm_powergate_samu()
1744 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); in kv_dpm_powergate_samu()
1745 kv_update_samu_dpm(adev, false); in kv_dpm_powergate_samu()
1749 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_acp() argument
1751 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp()
1756 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1762 kv_update_acp_dpm(adev, true); in kv_dpm_powergate_acp()
1764 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); in kv_dpm_powergate_acp()
1767 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); in kv_dpm_powergate_acp()
1768 kv_update_acp_dpm(adev, false); in kv_dpm_powergate_acp()
1772 static void kv_set_valid_clock_range(struct amdgpu_device *adev, in kv_set_valid_clock_range() argument
1776 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range()
1779 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1834 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, in kv_update_dfs_bypass_settings() argument
1838 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings()
1845 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_dfs_bypass_settings()
1857 static int kv_enable_nb_dpm(struct amdgpu_device *adev, in kv_enable_nb_dpm() argument
1860 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm()
1865 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); in kv_enable_nb_dpm()
1871 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); in kv_enable_nb_dpm()
1884 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_force_performance_level() local
1887 ret = kv_force_dpm_highest(adev); in kv_dpm_force_performance_level()
1891 ret = kv_force_dpm_lowest(adev); in kv_dpm_force_performance_level()
1895 ret = kv_unforce_levels(adev); in kv_dpm_force_performance_level()
1900 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_pre_set_power_state() local
1908 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state()
1909 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
1912 kv_update_requested_ps(adev, new_ps); in kv_dpm_pre_set_power_state()
1914 kv_apply_state_adjust_rules(adev, in kv_dpm_pre_set_power_state()
1923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_set_power_state() local
1924 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state()
1930 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); in kv_dpm_set_power_state()
1937 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1939 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1940 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1941 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1946 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1947 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1948 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1949 kv_enable_new_levels(adev); in kv_dpm_set_power_state()
1950 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1951 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1952 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1953 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1954 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1955 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1957 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1962 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1963 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
1964 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1968 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1969 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1970 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1975 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1976 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1977 kv_freeze_sclk_dpm(adev, true); in kv_dpm_set_power_state()
1978 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1979 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1980 kv_freeze_sclk_dpm(adev, false); in kv_dpm_set_power_state()
1981 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1982 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1987 kv_update_acp_boot_level(adev); in kv_dpm_set_power_state()
1988 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1989 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_post_set_power_state() local
1999 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state()
2002 kv_update_current_ps(adev, new_ps); in kv_dpm_post_set_power_state()
2005 static void kv_dpm_setup_asic(struct amdgpu_device *adev) in kv_dpm_setup_asic() argument
2007 sumo_take_smu_control(adev, true); in kv_dpm_setup_asic()
2008 kv_init_powergate_state(adev); in kv_dpm_setup_asic()
2009 kv_init_sclk_t(adev); in kv_dpm_setup_asic()
2013 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2015 struct kv_power_info *pi = kv_get_pi(adev);
2017 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2018 kv_force_lowest_valid(adev);
2019 kv_init_graphics_levels(adev);
2020 kv_program_bootup_state(adev);
2021 kv_upload_dpm_settings(adev);
2022 kv_force_lowest_valid(adev);
2023 kv_unforce_levels(adev);
2025 kv_init_graphics_levels(adev);
2026 kv_program_bootup_state(adev);
2027 kv_freeze_sclk_dpm(adev, true);
2028 kv_upload_dpm_settings(adev);
2029 kv_freeze_sclk_dpm(adev, false);
2030 kv_set_enabled_level(adev, pi->graphics_boot_level);
2035 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, in kv_construct_max_power_limits_table() argument
2038 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table()
2045 kv_convert_2bit_index_to_voltage(adev, in kv_construct_max_power_limits_table()
2052 static void kv_patch_voltage_values(struct amdgpu_device *adev) in kv_patch_voltage_values() argument
2056 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2058 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2060 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2062 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2067 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2074 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2081 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2088 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2094 static void kv_construct_boot_state(struct amdgpu_device *adev) in kv_construct_boot_state() argument
2096 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state()
2108 static int kv_force_dpm_highest(struct amdgpu_device *adev) in kv_force_dpm_highest() argument
2113 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_highest()
2122 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2123 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_highest()
2125 return kv_set_enabled_level(adev, i); in kv_force_dpm_highest()
2128 static int kv_force_dpm_lowest(struct amdgpu_device *adev) in kv_force_dpm_lowest() argument
2133 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_lowest()
2142 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2143 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_lowest()
2145 return kv_set_enabled_level(adev, i); in kv_force_dpm_lowest()
2148 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, in kv_get_sleep_divider_id_from_clock() argument
2151 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock()
2171 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) in kv_get_high_voltage_limit() argument
2173 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit()
2175 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2181 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= in kv_get_high_voltage_limit()
2193 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= in kv_get_high_voltage_limit()
2205 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, in kv_apply_state_adjust_rules() argument
2210 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules()
2216 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2219 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2222 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2223 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2249 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2250 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2264 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2265 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2276 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2277 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2298 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2311 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2321 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, in kv_dpm_power_level_enabled_for_throttle() argument
2324 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle()
2329 static int kv_calculate_ds_divider(struct amdgpu_device *adev) in kv_calculate_ds_divider() argument
2331 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider()
2340 kv_get_sleep_divider_id_from_clock(adev, in kv_calculate_ds_divider()
2347 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) in kv_calculate_nbps_level_settings() argument
2349 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings()
2353 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2359 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
2370 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2401 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) in kv_calculate_dpm_settings() argument
2403 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings()
2415 static void kv_init_graphics_levels(struct amdgpu_device *adev) in kv_init_graphics_levels() argument
2417 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels()
2420 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2429 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) in kv_init_graphics_levels()
2432 kv_set_divider_value(adev, i, table->entries[i].clk); in kv_init_graphics_levels()
2433 vid_2bit = kv_convert_vid7_to_vid2(adev, in kv_init_graphics_levels()
2436 kv_set_vid(adev, i, vid_2bit); in kv_init_graphics_levels()
2437 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2438 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2449 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) in kv_init_graphics_levels()
2452 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); in kv_init_graphics_levels()
2453 kv_set_vid(adev, i, table->entries[i].vid_2bit); in kv_init_graphics_levels()
2454 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2455 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2461 kv_dpm_power_level_enable(adev, i, false); in kv_init_graphics_levels()
2464 static void kv_enable_new_levels(struct amdgpu_device *adev) in kv_enable_new_levels() argument
2466 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels()
2471 kv_dpm_power_level_enable(adev, i, true); in kv_enable_new_levels()
2475 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) in kv_set_enabled_level() argument
2479 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_level()
2484 static int kv_set_enabled_levels(struct amdgpu_device *adev) in kv_set_enabled_levels() argument
2486 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels()
2492 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_levels()
2497 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, in kv_program_nbps_index_settings() argument
2501 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings()
2504 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_program_nbps_index_settings()
2521 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, in kv_set_thermal_temperature_range() argument
2544 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2545 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2559 static int kv_parse_sys_info_table(struct amdgpu_device *adev) in kv_parse_sys_info_table() argument
2561 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table()
2562 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_sys_info_table()
2609 sumo_construct_sclk_voltage_mapping_table(adev, in kv_parse_sys_info_table()
2613 sumo_construct_vid_mapping_table(adev, in kv_parse_sys_info_table()
2617 kv_construct_max_power_limits_table(adev, in kv_parse_sys_info_table()
2618 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2644 static void kv_patch_boot_state(struct amdgpu_device *adev, in kv_patch_boot_state() argument
2647 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state()
2653 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_non_clock_info() argument
2673 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2674 kv_patch_boot_state(adev, ps); in kv_parse_pplib_non_clock_info()
2677 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2680 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_clock_info() argument
2684 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info()
2702 static int kv_parse_power_table(struct amdgpu_device *adev) in kv_parse_power_table() argument
2704 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_power_table()
2724 amdgpu_add_thermal_controller(adev); in kv_parse_power_table()
2736 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2739 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2750 kfree(adev->pm.dpm.ps); in kv_parse_power_table()
2753 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2765 kv_parse_pplib_clock_info(adev, in kv_parse_power_table()
2766 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2770 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2775 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2778 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in kv_parse_power_table()
2780 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2785 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2786 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2792 static int kv_dpm_init(struct amdgpu_device *adev) in kv_dpm_init() argument
2800 adev->pm.dpm.priv = pi; in kv_dpm_init()
2802 ret = amdgpu_get_platform_caps(adev); in kv_dpm_init()
2806 ret = amdgpu_parse_extended_power_table(adev); in kv_dpm_init()
2827 if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) in kv_dpm_init()
2841 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2843 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2844 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2845 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2848 ret = kv_parse_sys_info_table(adev); in kv_dpm_init()
2852 kv_patch_voltage_values(adev); in kv_dpm_init()
2853 kv_construct_boot_state(adev); in kv_dpm_init()
2855 ret = kv_parse_power_table(adev); in kv_dpm_init()
2868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_debugfs_print_current_performance_level() local
2869 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level()
2884 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); in kv_dpm_debugfs_print_current_performance_level()
2898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_print_power_state() local
2907 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); in kv_dpm_print_power_state()
2909 amdgpu_dpm_print_ps_status(adev, rps); in kv_dpm_print_power_state()
2912 static void kv_dpm_fini(struct amdgpu_device *adev) in kv_dpm_fini() argument
2916 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2917 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2919 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2920 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2921 amdgpu_free_extended_power_table(adev); in kv_dpm_fini()
2931 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_sclk() local
2932 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk()
2943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_mclk() local
2944 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk()
2954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_get_temp() local
2970 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_early_init() local
2972 adev->powerplay.pp_funcs = &kv_dpm_funcs; in kv_dpm_early_init()
2973 adev->powerplay.pp_handle = adev; in kv_dpm_early_init()
2974 kv_dpm_set_irq_funcs(adev); in kv_dpm_early_init()
2982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_late_init() local
2984 if (!adev->pm.dpm_enabled) in kv_dpm_late_init()
2987 kv_dpm_powergate_acp(adev, true); in kv_dpm_late_init()
2988 kv_dpm_powergate_samu(adev, true); in kv_dpm_late_init()
2996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_init() local
2998 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, in kv_dpm_sw_init()
2999 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3003 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, in kv_dpm_sw_init()
3004 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3009 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3010 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3011 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3012 adev->pm.default_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3013 adev->pm.default_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3014 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3015 adev->pm.current_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3016 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in kv_dpm_sw_init()
3021 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3022 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_init()
3023 ret = kv_dpm_init(adev); in kv_dpm_sw_init()
3026 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3028 amdgpu_pm_print_power_states(adev); in kv_dpm_sw_init()
3029 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3035 kv_dpm_fini(adev); in kv_dpm_sw_init()
3036 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_fini() local
3045 flush_work(&adev->pm.dpm.thermal.work); in kv_dpm_sw_fini()
3047 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_fini()
3048 kv_dpm_fini(adev); in kv_dpm_sw_fini()
3049 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_fini()
3057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_init() local
3062 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_init()
3063 kv_dpm_setup_asic(adev); in kv_dpm_hw_init()
3064 ret = kv_dpm_enable(adev); in kv_dpm_hw_init()
3066 adev->pm.dpm_enabled = false; in kv_dpm_hw_init()
3068 adev->pm.dpm_enabled = true; in kv_dpm_hw_init()
3069 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_init()
3070 amdgpu_pm_compute_clocks(adev); in kv_dpm_hw_init()
3076 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_fini() local
3078 if (adev->pm.dpm_enabled) { in kv_dpm_hw_fini()
3079 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_fini()
3080 kv_dpm_disable(adev); in kv_dpm_hw_fini()
3081 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_fini()
3089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_suspend() local
3091 if (adev->pm.dpm_enabled) { in kv_dpm_suspend()
3092 mutex_lock(&adev->pm.mutex); in kv_dpm_suspend()
3094 kv_dpm_disable(adev); in kv_dpm_suspend()
3096 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3097 mutex_unlock(&adev->pm.mutex); in kv_dpm_suspend()
3105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_resume() local
3107 if (adev->pm.dpm_enabled) { in kv_dpm_resume()
3109 mutex_lock(&adev->pm.mutex); in kv_dpm_resume()
3110 kv_dpm_setup_asic(adev); in kv_dpm_resume()
3111 ret = kv_dpm_enable(adev); in kv_dpm_resume()
3113 adev->pm.dpm_enabled = false; in kv_dpm_resume()
3115 adev->pm.dpm_enabled = true; in kv_dpm_resume()
3116 mutex_unlock(&adev->pm.mutex); in kv_dpm_resume()
3117 if (adev->pm.dpm_enabled) in kv_dpm_resume()
3118 amdgpu_pm_compute_clocks(adev); in kv_dpm_resume()
3139 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, in kv_dpm_set_interrupt_state() argument
3187 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, in kv_dpm_process_interrupt() argument
3199 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3204 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3212 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_check_state_equal() local
3250 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) in kv_check_state_equal()
3284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_read_sensor() local
3285 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor()
3307 *((uint32_t *)value) = kv_dpm_get_temp(adev); in kv_dpm_read_sensor()
3379 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) in kv_dpm_set_irq_funcs() argument
3381 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3382 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()