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/Linux-v5.15/include/video/
Ds1d13xxxfb.h20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
[all …]
/Linux-v5.15/drivers/media/platform/atmel/
Datmel-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
60 /* ISC Clock Enable Register */
63 /* ISC Clock Disable Register */
66 /* ISC Clock Status Register */
72 /* ISC Clock Configuration Register */
[all …]
/Linux-v5.15/drivers/pinctrl/
Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
22 #define PIO_CODR 0x34 /* Clear Output Data Register */
23 #define PIO_ODSR 0x38 /* Output Data Status Register */
24 #define PIO_PDSR 0x3c /* Pin Data Status Register */
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Dpinctrl-equilibrium.h9 /* PINPAD register offset */
10 #define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
11 #define REG_PUEN 0x80 /* PULL UP Enable Register */
12 #define REG_PDEN 0x84 /* PULL DOWN Enable Register */
13 #define REG_SRC 0x88 /* Slew Rate Control Register */
14 #define REG_DCC0 0x8C /* Drive Current Control Register 0 */
15 #define REG_DCC1 0x90 /* Drive Current Control Register 1 */
16 #define REG_OD 0x94 /* Open Drain Enable Register */
17 #define REG_AVAIL 0x98 /* Pad Control Availability Register */
18 #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
[all …]
/Linux-v5.15/arch/arm/mach-sa1100/
Djornada720.c56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/Linux-v5.15/include/linux/fsl/
Dguts.h3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
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/Linux-v5.15/drivers/crypto/ux500/cryp/
Dcryp_irqp.h20 * 00h | CRYP_CR | Configuration register
22 * 04h | CRYP_SR | Status register
24 * 08h | CRYP_DIN | Data In register
26 * 0ch | CRYP_DOUT | Data out register
28 * 10h | CRYP_DMACR | DMA control register
41 * Refer data structure for other register map
46 * @cr - Configuration register
47 * @status - Status register
48 * @din - Data input register
49 * @din_size - Data input size register
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/Linux-v5.15/include/soc/fsl/qe/
Dimmap_qe.h23 __be32 iadd; /* I-RAM Address Register */
24 __be32 idata; /* I-RAM Data Register */
26 __be32 iready; /* I-RAM Ready Register */
55 __be32 cecr; /* QE command register */
56 __be32 ceccr; /* QE controller configuration register */
57 __be32 cecdr; /* QE command data register */
59 __be16 ceter; /* QE timer event register */
61 __be16 cetmr; /* QE timers mask register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
[all …]
/Linux-v5.15/arch/arm/mach-pxa/
Dpxa27x-udc.h9 #define UDCCR __REG(0x40600000) /* UDC Control Register */
48 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
49 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
57 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
85 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
86 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
104 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
114 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
115 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
116 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
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/Linux-v5.15/include/linux/mfd/da9052/
Dreg.h3 * Register declarations for DA9052 PMICs.
23 /* PARK REGISTER */
178 /* STATUS REGISTER A BITS */
188 /* STATUS REGISTER B BITS */
198 /* STATUS REGISTER C BITS */
208 /* STATUS REGISTER D BITS */
218 /* EVENT REGISTER A BITS */
228 /* EVENT REGISTER B BITS */
238 /* EVENT REGISTER C BITS */
248 /* EVENT REGISTER D BITS */
[all …]
/Linux-v5.15/arch/powerpc/include/asm/
Dmpic_msgr.h23 /* Get a message register
25 * @reg_num: the MPIC message register to get
27 * A pointer to the message register is returned. If
28 * the message register asked for is already in use, then
30 * with an actual message register, then ENODEV is returned.
31 * Successfully getting the register marks it as in use.
35 /* Relinquish a message register
37 * @msgr: the message register to return
39 * Disables the given message register and marks it as free.
41 * register is available to be acquired by a call to
[all …]
Dmpc5121.h11 u32 rcwlr; /* Reset Configuration Word Low Register */
12 u32 rcwhr; /* Reset Configuration Word High Register */
15 u32 rsr; /* Reset Status Register */
16 u32 rmr; /* Reset Mode Register */
17 u32 rpr; /* Reset Protection Register */
18 u32 rcr; /* Reset Control Register */
19 u32 rcer; /* Reset Control Enable Register */
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
[all …]
Dipic.h26 #define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
27 #define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
28 #define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
29 #define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
30 #define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
31 #define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
32 #define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
33 #define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
34 #define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
35 #define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
[all …]
Dreg_booke.h3 * Contains register definitions common to the Book E PowerPC
17 /* Machine State Register (MSR) Fields */
54 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
55 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
56 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
57 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
58 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
59 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
60 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
61 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
[all …]
/Linux-v5.15/include/linux/mfd/
Dtps65910.h126 * List of register bitfields for component TPS65910
142 /*Register BCK1 (0x80) register.RegisterDescription */
147 /*Register BCK2 (0x80) register.RegisterDescription */
152 /*Register BCK3 (0x80) register.RegisterDescription */
157 /*Register BCK4 (0x80) register.RegisterDescription */
162 /*Register BCK5 (0x80) register.RegisterDescription */
167 /*Register PUADEN (0x80) register.RegisterDescription */
186 /*Register REF (0x80) register.RegisterDescription */
193 /*Register VRTC (0x80) register.RegisterDescription */
200 /*Register VIO (0x80) register.RegisterDescription */
[all …]
/Linux-v5.15/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-txcommon.h9 /* Register definitions for TX_P2 */
13 * Core Register Definitions
16 /* Device ID Low Byte Register */
19 /* Device ID High Byte Register */
22 /* Device version register */
25 /* Power Down Control Register */
34 /* Reset Control Register 1 */
45 /* Reset Control Register 2 */
51 /* Video Control Register 1 */
58 /* Video Control Register 2 */
[all …]
Danalogix-i2c-dptx.h12 /* Register definitions for TX_P0 */
15 /* HDCP Status Register */
20 /* HDCP Control Register 0 */
32 /* HDCP Receiver BSTATUS Register 0 */
34 /* HDCP Receiver BSTATUS Register 1 */
42 /* HDCP Wait R0 Timing Register */
45 /* HDCP Link Integrity Check Timer Register */
48 /* HDCP Repeater Ready Wait Timer Register */
51 /* HDCP Auto Timer Register */
54 /* HDCP Key Status Register */
[all …]
/Linux-v5.15/drivers/net/ethernet/sun/
Dsungem.h12 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
13 #define GREG_CFG 0x0004UL /* Configuration Register */
14 #define GREG_STAT 0x000CUL /* Status Register */
15 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
16 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
18 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
19 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
20 #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
21 #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
22 #define GREG_SWRST 0x1010UL /* Software Reset Register */
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/Linux-v5.15/drivers/scsi/aic7xxx/
Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
50 /* Register window Modes */
88 * is added to the register which is referenced in the driver.
89 * Unreferenced register with no dont_generate_debug_code will result
96 * as the source and destination of any register accesses in our
97 * register window.
99 register MODE_PTR {
114 register INTSTAT {
131 register SEQINTCODE {
211 register CLRINT {
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/Linux-v5.15/arch/arm/mach-pxa/include/mach/
Dregs-uart.h11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
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/Linux-v5.15/arch/powerpc/sysdev/
Dfsl_pci.h15 /* FSL PCI controller BRR1 register */
39 __be32 potar; /* 0x.0 - Outbound translation address register */
40 __be32 potear; /* 0x.4 - Outbound translation extended address register */
41 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 __be32 powar; /* 0x.10 - Outbound window attributes register */
49 __be32 pitar; /* 0x.0 - Inbound translation address register */
51 __be32 piwbar; /* 0x.8 - Inbound window base address register */
52 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
53 __be32 piwar; /* 0x.10 - Inbound window attributes register */
59 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
[all …]
/Linux-v5.15/arch/sh/include/mach-common/mach/
Durquell.h20 * CS7 | SH7786 register
34 #define SRSTR_OFS 0x0000 /* System reset register */
36 #define IRL0SR_OFS 0x0020 /* IRL0 Status register */
37 #define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
38 #define IRL1SR_OFS 0x0040 /* IRL1 Status register */
39 #define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
40 #define IRL2SR_OFS 0x0060 /* IRL2 Status register */
41 #define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
42 #define IRL3SR_OFS 0x0080 /* IRL3 Status register */
43 #define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
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/Linux-v5.15/drivers/net/wireless/ath/ath5k/
Dreg.h21 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
32 * This file also contains register values found on a memory dump of
50 * Mac Control Register
52 #define AR5K_CR 0x0008 /* Register Address */
62 * RX Descriptor Pointer register
67 * Configuration and status register
69 #define AR5K_CFG 0x0014 /* Register Address */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
87 * Interrupt enable register
89 #define AR5K_IER 0x0024 /* Register Address */
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/Linux-v5.15/arch/mips/include/asm/sibyte/
Dsb1250_uart.h30 * DUART Mode Register #1 (Table 10-3)
31 * Register: DUART_MODE_REG_1_A
32 * Register: DUART_MODE_REG_1_B
74 * DUART Mode Register #2 (Table 10-4)
75 * Register: DUART_MODE_REG_2_A
76 * Register: DUART_MODE_REG_2_B
102 * DUART Command Register (Table 10-5)
103 * Register: DUART_CMD_A
104 * Register: DUART_CMD_B
137 * DUART Status Register (Table 10-6)
[all …]

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