Lines Matching full:register

12 /* Register definitions for TX_P0                              */
15 /* HDCP Status Register */
20 /* HDCP Control Register 0 */
32 /* HDCP Receiver BSTATUS Register 0 */
34 /* HDCP Receiver BSTATUS Register 1 */
42 /* HDCP Wait R0 Timing Register */
45 /* HDCP Link Integrity Check Timer Register */
48 /* HDCP Repeater Ready Wait Timer Register */
51 /* HDCP Auto Timer Register */
54 /* HDCP Key Status Register */
57 /* HDCP Key Command Register */
71 /* Bits for DP System Control Register 2 */
73 /* Bits for DP System Control Register 3 */
80 /* Bits for DP System Control Register 4 */
83 /* DP Video Control Register */
94 /* DP Audio Control Register */
102 /* Packet Send Control Register */
113 /* DP HDCP Control Register */
119 /* DP Main Link Bandwidth Setting Register */
124 /* DP Lane Count Setting Register */
127 /* DP Training Pattern Set Register */
130 /* DP Lane 0 Link Training Control Register */
138 /* DP Link Training Control Register */
155 /* DP Debug Register 1 */
160 /* DP Polling Control Register */
164 /* DP Link Debug Control Register */
171 /* AUX Misc control Register */
174 /* DP PLL control Register */
178 /* DP Analog Power Down Register */
182 /* DP Misc Control Register */
186 /* DP Extra I2C Device Address Register */
192 /* DP Downspread Control Register 1 */
195 /* DP M Value Calculation Control Register */
199 /* AUX Channel Access Status Register */
203 /* AUX Channel DEFER Control Register */
207 /* DP Buffer Data Count Register */
212 /* DP AUX Channel Control Register 1 */
218 /* DP AUX CH Address Register 0 */
221 /* DP AUX CH Address Register 1 */
224 /* DP AUX CH Address Register 2 */
228 /* DP AUX Channel Control Register 2 */
236 /* DP Video Stream Control InfoFrame Register */
240 /* DP Video Stream Data Byte 1 Register */
243 /* DP AUX Channel Control Register 3 */
247 /* DP AUX Channel Control Register 4 */