Lines Matching full:register
21 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
32 * This file also contains register values found on a memory dump of
50 * Mac Control Register
52 #define AR5K_CR 0x0008 /* Register Address */
62 * RX Descriptor Pointer register
67 * Configuration and status register
69 #define AR5K_CFG 0x0014 /* Register Address */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
87 * Interrupt enable register
89 #define AR5K_IER 0x0024 /* Register Address */
95 * 0x0028 is Beacon Control Register on 5210
96 * and first RTS duration register on 5211
100 * Beacon control register [5210]
102 #define AR5K_BCR 0x0028 /* Register Address */
111 * First RTS duration register [5211]
113 #define AR5K_RTSD0 0x0028 /* Register Address */
125 * 0x002c is Beacon Status Register on 5210
126 * and second RTS duration register on 5211
130 * Beacon status register [5210]
133 * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
134 * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
139 #define AR5K_BSR 0x002c /* Register Address */
152 * Second RTS duration register [5211]
154 #define AR5K_RTSD1 0x002c /* Register Address */
166 * Transmit configuration register
168 #define AR5K_TXCFG 0x0030 /* Register Address */
193 * Receive configuration register
195 #define AR5K_RXCFG 0x0034 /* Register Address */
205 * Receive jumbo descriptor last address register
211 * MIB control register
213 #define AR5K_MIBC 0x0040 /* Register Address */
220 * Timeout prescale register
226 * Receive timeout register (no frame received)
232 * Transmit timeout register (no frame sent)
240 * Receive frame gap timeout register
246 * Receive frame count limit register
253 * Misc settings register
256 #define AR5K_MISC 0x0058 /* Register Address */
269 * QCU/DCU clock gating register (5311)
272 #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */
279 * For 5210 there is only one status register but for
288 #define AR5K_ISR 0x001c /* Register Address [5210] */
289 #define AR5K_PISR 0x0080 /* Register Address [5211+] */
302 * TXNOFRM_QCU field on TXNOFRM register */
341 #define AR5K_SISR0 0x0084 /* Register Address [5211+] */
347 #define AR5K_SISR1 0x0088 /* Register Address [5211+] */
353 #define AR5K_SISR2 0x008c /* Register Address [5211+] */
367 #define AR5K_SISR3 0x0090 /* Register Address [5211+] */
373 #define AR5K_SISR4 0x0094 /* Register Address [5211+] */
393 #define AR5K_IMR 0x0020 /* Register Address [5210] */
394 #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */
432 #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */
438 #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */
444 #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */
458 #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
464 #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */
480 * Wake On Wireless pattern control register [5212+]
482 #define AR5K_WOW_PCFG 0x0410 /* Register Address */
494 * Wake On Wireless pattern index register (?) [5212+]
499 * Wake On Wireless pattern data register [5212+]
501 #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */
512 #define AR5K_DCCFG 0x0420 /* Register Address */
521 #define AR5K_CCFG 0x0600 /* Register Address */
525 #define AR5K_CCFG_CCU 0x0604 /* Register Address */
548 * configuration register (0x08c0 - 0x08ec), a ready time configuration
549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
558 * Generic QCU Register access macros
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
571 * QCU Transmit enable register
578 * QCU Transmit disable register
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
646 * QCU ready time shutdown register
659 * QCU compression buffer configuration register [5212+]
672 * QCU registers in pairs. For each queue we have a QCU mask register,
673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
674 * a retry limit register (0x1080 - 0x10ac), a channel time register
675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
676 * a sequence number register (0x1140 - 0x116c). It seems that "global"
678 * We use the same macros here for easier register access.
685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
690 * DCU local Inter Frame Space settings register
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
773 * DCU global IFS SIFS register
779 * DCU global IFS slot interval register
785 * DCU global IFS EIFS register
791 * DCU global IFS misc register
793 * LFSR stands for Linear Feedback Shift Register
800 #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
813 * DCU frame prefetch control register
815 #define AR5K_DCU_FP 0x1230 /* Register Address */
821 * DCU transmit pause control/status register
823 #define AR5K_DCU_TXP 0x1270 /* Register Address */
842 * DCU clear transmit filter register
847 * DCU set transmit filter register
852 * Reset control register
854 #define AR5K_RESET_CTL 0x4000 /* Register Address */
863 * Sleep control register
865 #define AR5K_SLEEP_CTL 0x4004 /* Register Address */
879 * Interrupt pending register
885 * Sleep force register
891 * PCI configuration register
894 #define AR5K_PCICFG 0x4010 /* Register Address */
930 * "General Purpose Input/Output" (GPIO) control register
947 #define AR5K_GPIOCR 0x4014 /* Register Address */
958 * "General Purpose Input/Output" (GPIO) data output register
963 * "General Purpose Input/Output" (GPIO) data input register
969 * Silicon revision register
971 #define AR5K_SREV 0x4020 /* Register Address */
978 * TXE write posting register
988 * register on 5414 and pm configuration register
993 * register (enable/disable) [5414]
1000 * and status register [5424+]
1002 #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
1020 * PCI-E Workaround enable register
1037 * read data register for 5210 is at 0x6800 and
1038 * status register is at 0x6c00. There is also
1039 * no eeprom command register on 5210 and the
1045 * check the eeprom status register
1046 * and read eeprom data register.
1050 * check the eeprom status register
1051 * and read eeprom data register.
1056 * check the eeprom status register
1059 * write data to data register
1061 * check the eeprom status register
1071 * EEPROM data register
1079 * EEPROM command register
1081 #define AR5K_EEPROM_CMD 0x6008 /* Register Address */
1087 * EEPROM status register
1089 #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */
1090 #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */
1099 * EEPROM config register
1101 #define AR5K_EEPROM_CFG 0x6010 /* Register Address */
1127 * Used for checking initial register writes
1134 * First station id register (Lower 32 bits of MAC address)
1140 * Second station id register (Upper 16 bits of MAC address + PCU settings)
1142 #define AR5K_STA_ID1 0x8004 /* Register Address */
1171 * First BSSID register (MAC address, lower 32bits)
1176 * Second BSSID register (MAC address in upper 16 bits)
1185 * Backoff slot time register
1190 * ACK/CTS timeout register
1192 #define AR5K_TIME_OUT 0x8014 /* Register Address */
1199 * RSSI threshold register
1201 #define AR5K_RSSI_THR 0x8018 /* Register Address */
1220 * Retry limit register
1222 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
1224 #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */
1237 * Transmit latency register
1239 #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */
1240 #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */
1257 * PCU beacon control register
1259 #define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */
1260 #define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */
1271 * CFP period register
1279 * Next beacon time register
1287 * Next DMA beacon alert register
1295 * Next software beacon alert register
1303 * Next ATIM window time register
1312 * 5210 First inter frame spacing register (IFS)
1321 * 5210 Second inter frame spacing register (IFS)
1332 * CFP duration register
1340 * Receive filter register
1342 #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */
1343 #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */
1366 * Multicast filter register (lower 32 bits)
1374 * Multicast filter register (higher 16 bits)
1383 * Transmit mask register (lower 32 bits) [5210]
1388 * Transmit mask register (higher 16 bits) [5210]
1398 * Trigger level register (before transmission) [5210]
1404 * PCU Diagnostic register
1408 #define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */
1409 #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */
1455 * TSF (clock) register (lower 32 bits)
1463 * TSF (clock) register (higher 32 bits)
1471 * Last beacon timestamp register (Read Only)
1476 * ADDAC test register [5211+]
1478 #define AR5K_ADDAC_TEST 0x8054 /* Register Address */
1492 * Default antenna register [5211+]
1497 * Frame control QoS mask register (?) [5211+]
1503 * Seq mask register (?) [5211+]
1508 * Retry count register [5210]
1510 #define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */
1515 * Back-off status register [5210]
1517 #define AR5K_BACKOFF 0x8088 /* Register Address [5210] */
1524 * NAV register (current)
1571 * Beacon count register
1582 * Transmit power control register
1595 * XR (eXtended Range) mode register
1597 #define AR5K_XRMODE 0x80c0 /* Register Address */
1608 * XR delay register
1610 #define AR5K_XRDELAY 0x80c4 /* Register Address */
1617 * XR timeout register
1619 #define AR5K_XRTIMEOUT 0x80c8 /* Register Address */
1626 * XR chirp register
1628 #define AR5K_XRCHIRP 0x80cc /* Register Address */
1633 * XR stomp register
1635 #define AR5K_XRSTOMP 0x80d0 /* Register Address */
1644 * First enhanced sleep register
1646 #define AR5K_SLEEP0 0x80d4 /* Register Address */
1655 * Second enhanced sleep register
1657 #define AR5K_SLEEP1 0x80d8 /* Register Address */
1664 * Third enhanced sleep register
1666 #define AR5K_SLEEP2 0x80dc /* Register Address */
1673 * TX power control (TPC) register
1678 #define AR5K_TXPC 0x80e8 /* Register Address */
1705 #define AR5K_QUIET_CTL1 0x80fc /* Register Address */
1711 #define AR5K_QUIET_CTL2 0x8100 /* Register Address */
1718 * TSF parameter register
1720 #define AR5K_TSF_PARM 0x8104 /* Register Address */
1727 #define AR5K_QOS_NOACK 0x8108 /* Register Address */
1736 * PHY error filter register
1744 * XR latency register
1749 * ACK SIFS register
1751 #define AR5K_ACKSIFS 0x8114 /* Register Address */
1755 * MIC QoS control register (?)
1757 #define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */
1762 * MIC QoS select register (?)
1768 * Misc mode control register (?)
1770 #define AR5K_MISC_MODE 0x8120 /* Register Address */
1799 * TSF Threshold register (?)
1811 #define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */
1852 #define AR5K_PHY_TST2 0x9800 /* Register Address */
1873 * PHY frame control register [5110] /turbo mode register [5111+]
1875 * There is another frame control register for [5111+]
1877 * are common here between 5110 frame control register
1878 * and [5111+] turbo mode register, so this also works as
1879 * a "turbo mode register" for 5110. We treat this one as
1880 * a frame control register for 5110 below.
1882 #define AR5K_PHY_TURBO 0x9804 /* Register Address */
1888 * PHY agility command register
1891 #define AR5K_PHY_AGC 0x9808 /* Register Address */
1902 * PHY timing register 3 [5112+]
1911 * PHY chip revision register
1916 * PHY activation register
1918 #define AR5K_PHY_ACT 0x981c /* Register Address */
1925 #define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */
1929 #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
1942 #define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */
1949 * Pre-Amplifier control register
1952 #define AR5K_PHY_PA_CTL 0x9838 /* Register Address */
1959 * PHY settling register
1961 #define AR5K_PHY_SETTLING 0x9844 /* Register Address */
1970 #define AR5K_PHY_GAIN 0x9848 /* Register Address */
1976 #define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */
1980 * Desired ADC/PGA size register
1983 #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */
1992 * PHY signal register
1995 #define AR5K_PHY_SIG 0x9858 /* Register Address */
2002 * PHY coarse agility control register
2005 #define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */
2012 * PHY agility control register
2014 #define AR5K_PHY_AGCCTL 0x9860 /* Register address */
2023 * PHY noise floor status register (CCA = Clear Channel Assessment)
2025 #define AR5K_PHY_NF 0x9864 /* Register address */
2034 * PHY ADC saturation register [5110]
2081 * PHY PLL (Phase Locked Loop) control register
2103 * RF Buffer register
2105 * It's obvious from the code that 0x989c is the buffer register but
2120 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */
2133 * PHY RF stage register [5210]
2152 * PHY Antenna control register
2154 #define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */
2162 * PHY receiver delay register [5111+]
2164 #define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */
2168 * PHY max rx length register (?) [5111]
2173 * PHY timing register 4
2174 * I(nphase)/Q(adrature) calibration register [5111+]
2176 #define AR5K_PHY_IQ 0x9920 /* Register Address */
2193 * PHY timing register 5
2197 #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
2207 * PHY-only warm reset register
2212 * PHY-only control register
2214 #define AR5K_PHY_CTL 0x992c /* Register Address */
2225 * PHY PAPD probe register [5111+]
2256 * PHY frame control register [5111+]
2286 * PHY Tx Power adjustment register [5212A+]
2295 * PHY radar detection register [5111+]
2338 * Sigma Delta register (?) [5213]
2351 * RF restart register [5112+] (?)
2358 * RF Bus access request register (for synth-only channel switching)
2387 #define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
2404 * PHY timing IQ calibration result register [5111+]
2411 * PHY current RSSI register [5111+]
2416 * PHY RF Bus grant register
2422 * PHY ADC test register
2429 * PHY DAC test register
2436 * PHY PTAT register (?)
2441 * PHY Illegal TX rate register [5112+]
2446 * PHY SPUR Power register [5112+]
2448 #define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */
2454 * PHY Channel status register [5112+] (?)
2463 * Heavy clip enable register
2491 * PHY mode register [5111+]
2493 #define AR5K_PHY_MODE 0x0a200 /* Register Address */
2509 * PHY CCK transmit control register [5111+ (?)]
2518 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
2529 * PHY 2GHz gain register [5111+]
2550 * Transmit Power Control register