Lines Matching full:register
3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
45 * Register
49 * Register
58 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
66 * Register
69 * Control Register
72 * Configuration Register
75 * Configuration Register
78 * register
80 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
82 * Control Register
84 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
85 u32 autorstsr; /* 0x.009c - Automatic reset status register */
86 u32 pvr; /* 0x.00a0 - Processor Version Register */
87 u32 svr; /* 0x.00a4 - System Version Register */
89 u32 rstcr; /* 0x.00b0 - Reset Control Register */
91 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
97 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
98 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
100 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
102 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
104 u32 ircr; /* 0x.0900 - Infrared Control Register */
106 u32 dmacr; /* 0x.0908 - DMA Control Register */
108 u32 elbccr; /* 0x.0914 - eLBC Control Register */
110 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
111 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
112 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
114 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
116 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
118 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
120 * register
123 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
124 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
127 * register
130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
143 * Set the DMACR register in the GUTS
145 * The DMACR register determines the source of initiated transfers for each
218 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
220 __be32 cdozcr; /* 0x000c Core Doze Control Register */
222 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
224 __be32 cnapcr; /* 0x001c Core Nap Control Register */
226 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
228 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
230 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
232 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
233 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
236 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
238 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
240 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
242 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
244 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
246 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
248 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
252 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
257 __be32 tph10sr0; /* Thread PH10 Status Register */
259 __be32 tph10setr0; /* Thread PH10 Set Control Register */
261 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
263 __be32 tph10psr0; /* Thread PH10 Previous Status Register */
265 __be32 twaitsr0; /* Thread Wait Status Register */
267 __be32 pcph15sr; /* Physical Core PH15 Status Register */
268 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
269 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
270 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
272 __be32 pcph20sr; /* Physical Core PH20 Status Register */
273 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
274 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
275 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
276 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
278 __be32 pcph30sr; /* Physical Core PH30 Status Register */
279 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
280 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
281 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
283 __be32 ippwrgatecr; /* IP Power Gating Control Register */
303 __be32 tbclkdivr; /* Time Base Clock Divider Register */
305 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
306 __be32 clpcl10sr; /* Cluster PCL10 Status Register */
307 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
308 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
309 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
310 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
311 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
312 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
313 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
314 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
315 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */
317 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */