Lines Matching full:register

9 /* PINPAD register offset */
10 #define REG_PMX_BASE	0x0	/* Port Multiplexer Control Register */
11 #define REG_PUEN	0x80	/* PULL UP Enable Register */
12 #define REG_PDEN	0x84	/* PULL DOWN Enable Register */
13 #define REG_SRC		0x88	/* Slew Rate Control Register */
14 #define REG_DCC0	0x8C	/* Drive Current Control Register 0 */
15 #define REG_DCC1	0x90	/* Drive Current Control Register 1 */
16 #define REG_OD		0x94	/* Open Drain Enable Register */
17 #define REG_AVAIL	0x98	/* Pad Control Availability Register */
18 #define DRV_CUR_PINS	16	/* Drive Current pin number per register */
21 /* GPIO register offset */
22 #define GPIO_OUT	0x0	/* Data Output Register */
23 #define GPIO_IN		0x4	/* Data Input Register */
24 #define GPIO_DIR	0x8	/* Direction Register */
25 #define GPIO_EXINTCR0	0x18	/* External Interrupt Control Register 0 */
26 #define GPIO_EXINTCR1	0x1C	/* External Interrupt Control Register 1 */
27 #define GPIO_IRNCR	0x20	/* IRN Capture Register */
28 #define GPIO_IRNICR	0x24	/* IRN Interrupt Control Register */
29 #define GPIO_IRNEN	0x28	/* IRN Interrupt Enable Register */
30 #define GPIO_IRNCFG	0x2C	/* IRN Interrupt Configuration Register */
31 #define GPIO_IRNRNSET	0x30	/* IRN Interrupt Enable Set Register */
32 #define GPIO_IRNENCLR	0x34	/* IRN Interrupt Enable Clear Register */
33 #define GPIO_OUTSET	0x40	/* Output Set Register */
34 #define GPIO_OUTCLR	0x44	/* Output Clear Register */
35 #define GPIO_DIRSET	0x48	/* Direction Set Register */
36 #define GPIO_DIRCLR	0x4C	/* Direction Clear Register */
84  * @membase: base address of the pin bank register.
107  * @lock: spin lock to protect gpio register write.
117 	raw_spinlock_t		lock; /* protect gpio register */
130  * @lock: protect pinctrl register write
141 	raw_spinlock_t			lock; /* protect pinpad register */