Lines Matching full:register
23 __be32 iadd; /* I-RAM Address Register */
24 __be32 idata; /* I-RAM Data Register */
26 __be32 iready; /* I-RAM Ready Register */
55 __be32 cecr; /* QE command register */
56 __be32 ceccr; /* QE controller configuration register */
57 __be32 cecdr; /* QE command data register */
59 __be16 ceter; /* QE timer event register */
61 __be16 cetmr; /* QE timers mask register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
64 __be32 cetsr2; /* QE time-stamp register 2 */
66 __be32 cevter; /* QE virtual tasks event register */
67 __be32 cevtmr; /* QE virtual tasks mask register */
68 __be16 cercr; /* QE RAM control register */
71 __be16 ceexe1; /* QE external request 1 event register */
73 __be16 ceexm1; /* QE external request 1 mask register */
75 __be16 ceexe2; /* QE external request 2 event register */
77 __be16 ceexm2; /* QE external request 2 mask register */
79 __be16 ceexe3; /* QE external request 3 event register */
81 __be16 ceexm3; /* QE external request 3 mask register */
83 __be16 ceexe4; /* QE external request 4 event register */
85 __be16 ceexm4; /* QE external request 4 mask register */
87 __be32 ceurnr; /* QE microcode revision number register */
93 __be32 cmxgcr; /* CMX general clock route register */
94 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
95 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
96 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
98 __be32 cmxupcr; /* CMX UPC clock route register */
104 u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/
106 u8 gtcfr2; /* Timer 3 and timer 4 global config register*/
108 __be16 gtmdr1; /* Timer 1 mode register */
109 __be16 gtmdr2; /* Timer 2 mode register */
110 __be16 gtrfr1; /* Timer 1 reference register */
111 __be16 gtrfr2; /* Timer 2 reference register */
112 __be16 gtcpr1; /* Timer 1 capture register */
113 __be16 gtcpr2; /* Timer 2 capture register */
116 __be16 gtmdr3; /* Timer 3 mode register */
117 __be16 gtmdr4; /* Timer 4 mode register */
118 __be16 gtrfr3; /* Timer 3 reference register */
119 __be16 gtrfr4; /* Timer 4 reference register */
120 __be16 gtcpr3; /* Timer 3 capture register */
121 __be16 gtcpr4; /* Timer 4 capture register */
124 __be16 gtevr1; /* Timer 1 event register */
125 __be16 gtevr2; /* Timer 2 event register */
126 __be16 gtevr3; /* Timer 3 event register */
127 __be16 gtevr4; /* Timer 4 event register */
128 __be16 gtps; /* Timer 1 prescale register */
141 __be32 spmode; /* SPI mode register */
143 u8 spie; /* SPI event register */
146 u8 spim; /* SPI mask register */
149 u8 spcom; /* SPI command register */
151 __be32 spitd; /* SPI transmit data register (cpu mode) */
152 __be32 spird; /* SPI receive data register (cpu mode) */
158 __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */
159 u8 siglmr1_h; /* SI1 global mode register high */
161 u8 sicmdr1_h; /* SI1 command register high */
163 u8 sistr1_h; /* SI1 status register high */
165 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
175 __be16 siemr1; /* SI1 TDME mode register 16 bits */
176 __be16 sifmr1; /* SI1 TDMF mode register 16 bits */
177 __be16 sigmr1; /* SI1 TDMG mode register 16 bits */
178 __be16 sihmr1; /* SI1 TDMH mode register 16 bits */
179 u8 siglmg1_l; /* SI1 global mode register low 8 bits */
181 u8 sicmdr1_l; /* SI1 command register low 8 bits */
183 u8 sistr1_l; /* SI1 status register low 8 bits */
185 __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/
195 __be32 siml1; /* SI1 multiframe limit register */
196 u8 siedm1; /* SI1 extended diagnostic mode register */
228 __be32 mcce; /* MCC event register */
229 __be32 mccm; /* MCC mask register */
230 __be32 mccf; /* MCC configuration register */
231 __be32 merl; /* MCC emergency request level register */
237 __be32 gumr_l; /* UCCx general mode register (low) */
238 __be32 gumr_h; /* UCCx general mode register (high) */
239 __be16 upsmr; /* UCCx protocol-specific mode register */
241 __be16 utodr; /* UCCx transmit on demand register */
242 __be16 udsr; /* UCCx data synchronization register */
243 __be16 ucce; /* UCCx event register */
245 __be16 uccm; /* UCCx mask register */
247 u8 uccs; /* UCCx status register */
251 u8 guemr; /* UCC general extended mode register */
256 __be32 gumr; /* UCCx general mode register */
257 __be32 upsmr; /* UCCx protocol-specific mode register */
258 __be16 utodr; /* UCCx transmit on demand register */
260 __be16 udsr; /* UCCx data synchronization register */
262 __be32 ucce; /* UCCx event register */
263 __be32 uccm; /* UCCx mask register */
264 u8 uccs; /* UCCx status register */
281 __be32 urtry; /* UCC retry counter register */
283 u8 guemr; /* UCC general extended mode register */
296 __be32 upgcr; /* UTOPIA/POS general configuration register */
298 __be32 uphec; /* ATM HEC register */
343 __be32 uper1; /* Device 1 port enable register */
344 __be32 uper2; /* Device 2 port enable register */
345 __be32 uper3; /* Device 3 port enable register */
346 __be32 uper4; /* Device 4 port enable register */
352 __be32 sdsr; /* Serial DMA status register */
353 __be32 sdmr; /* Serial DMA mode register */
354 __be32 sdtr1; /* SDMA system bus threshold register */
355 __be32 sdtr2; /* SDMA secondary bus threshold register */
356 __be32 sdhy1; /* SDMA system bus hysteresis register */
357 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
358 __be32 sdta1; /* SDMA system bus address register */
359 __be32 sdta2; /* SDMA secondary bus address register */
360 __be32 sdtm1; /* SDMA system bus MSNUM register */
361 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
363 __be32 sdaqr; /* SDMA address bus qualify register */
364 __be32 sdaqmr; /* SDMA address bus qualify mask register */
366 __be32 sdebcr; /* SDMA CAM entries base register */
372 __be32 bpdcr; /* Breakpoint debug command register */
373 __be32 bpdsr; /* Breakpoint debug status register */
374 __be32 bpdmr; /* Breakpoint debug mask register */
375 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
376 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
378 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
379 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
381 __be32 bprmir; /* Breakpoint request mode immediate register */
382 __be32 bprmsr; /* Breakpoint request mode serial register */
383 __be32 bpemr; /* Breakpoint exit mode register */
417 __be32 eccr; /* Exception control configuration register */