| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gfx.c | 31 /* delay 0.1 second to enable gfx off feature */
35 * GPU GFX IP block helpers function.
43 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
44 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
56 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
[all …]
|
| D | amdgpu_rlc.c | 39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
|
| D | gfx_v6_0.c | 341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
[all …]
|
| D | gfx_v7_0.c | 930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
[all …]
|
| D | gfx_v8_0.c | 831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
932 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
933 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
934 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
935 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
936 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
937 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
938 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
[all …]
|
| D | gfx_v9_0.c | 47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
932 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
995 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
996 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
997 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1130 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1131 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1132 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1133 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1134 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
[all …]
|
| D | gfx_v10_0.c | 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3332 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3407 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
3408 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
3409 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
3548 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3549 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3550 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3551 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3552 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
[all …]
|
| D | amdgpu_discovery.c | 389 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); in amdgpu_discovery_get_gfx_info()
390 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
392 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
393 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
394 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
395 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); in amdgpu_discovery_get_gfx_info()
396 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
397 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
398 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
399 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
[all …]
|
| D | amdgpu_kms.c | 243 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
244 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
247 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
248 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
251 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
252 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
255 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
256 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
259 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
260 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
|
| D | amdgpu_gfx.h | 28 * GFX stuff
34 /* GFX current status */
118 * GFX configurations
176 /* gfx configure feature */
301 /* gfx status */
312 /* gfx off */
315 … gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: ad…
326 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
327 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se…
328 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((a…
[all …]
|
| D | amdgpu_ucode.c | 98 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
110 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
420 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
421 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
422 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
423 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
424 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
425 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
426 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
427 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
[all …]
|
| D | amdgpu_amdkfd.c | 126 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
127 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
140 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
147 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
148 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
359 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
362 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
365 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
368 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
371 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
|
| D | amdgpu_amdkfd_gfx_v9.c | 74 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
75 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
83 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
127 * need to do this twice, once for gfx and once for mmhub in kgd_gfx_v9_set_pasid_vmid_mapping()
178 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
179 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
319 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
328 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
329 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
334 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
[all …]
|
| D | amdgpu_atomfirmware.c | 477 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
478 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
479 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
480 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
481 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
482 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
483 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
484 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
485 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
487 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
[all …]
|
| D | amdgpu_debugfs.c | 243 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
244 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
679 * amdgpu_debugfs_gca_config_read - Read from gfx config data
709 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
710 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
711 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
712 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
713 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
714 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
715 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
[all …]
|
| D | psp_gfx_if.h | 37 /* TEE Gfx Command IDs for the register interface.
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
63 /* Control registers of the TEE Gfx interface. These are located in
68 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
82 * When PSP GFX I/F is initialized, the flag is set.
86 /* TEE Gfx Command IDs for the ring buffer interface. */
274 /* All GFX ring buffer commands. */
288 /* Structure of GFX Response buffer.
298 …uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to…
|
| D | amdgpu_amdkfd_gfx_v10_3.c | 69 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
70 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
78 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
115 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n", in set_pasid_vmid_mapping_v10_3()
128 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
129 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
211 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
212 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
295 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
304 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
[all …]
|
| D | amdgpu_virt.c | 63 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
492 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
493 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
494 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
495 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
496 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
497 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
498 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
499 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
500 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
|
| /Linux-v5.10/Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 1 Device tree configuration for the GFX display device on the ASPEED SoCs
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
17 - resets: reset line that must be released to use the GFX device
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
|
| /Linux-v5.10/Documentation/devicetree/bindings/mfd/ |
| D | aspeed-gfx.txt | 1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
8 - compatible: "aspeed,ast2500-gfx", "syscon"
9 - reg: contains offset/length value of the GFX memory
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/include/ |
| D | dal_asic_id.h | 74 /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
77 /* KV2 with Spooky GFX core, including downgraded from Spectre core,
81 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
84 /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
87 /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
90 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
93 /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
|
| /Linux-v5.10/drivers/gpu/drm/aspeed/ |
| D | aspeed_gfx_drv.c | 30 * DOC: ASPEED GFX Driver
32 * This driver is for the ASPEED BMC SoC's 'GFX' display hardware, also called
176 aspeed_gfx_irq_handler, 0, "aspeed gfx", drm); in aspeed_gfx_load()
203 .name = "aspeed-gfx-drm",
204 .desc = "ASPEED GFX DRM",
211 { .compatible = "aspeed,ast2500-gfx" },
|
| /Linux-v5.10/arch/x86/platform/atom/ |
| D | punit_atom_debug.c | 58 { "GFX RENDER", PWRGT_STATUS, RENDER_POS },
59 { "GFX MEDIA", PWRGT_STATUS, MEDIA_POS },
68 { "GFX RENDER", PWRGT_STATUS, RENDER_POS },
69 { "GFX MEDIA", PWRGT_STATUS, MEDIA_POS },
|
| /Linux-v5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2500-pinctrl.yaml | 35 0: compatible with "aspeed,ast2500-gfx", "syscon"
85 aspeed,external-nodes = <&gfx>, <&lhc>;
99 gfx: display@1e6e6000 {
100 compatible = "aspeed,ast2500-gfx", "syscon";
|
| /Linux-v5.10/drivers/gpu/drm/amd/include/ |
| D | amd_acpi.h | 47 u8 thermal_gfx; /* thermal state: target gfx controller */
49 u8 forced_power_gfx; /* forced power state: target gfx controller */
111 * ATIF provides an entry point for the gfx driver to interact with the sbios.
201 * BYTE - thermal state: target gfx controller
203 * BYTE - forced power state: target gfx controller
207 * BYTE - GPU package power limit: target gfx controller
217 /* target gfx controller */
230 * WORD - gfx controller id
275 * WORD - number of reported external gfx devices
|
