243 		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||  in amdgpu_debugfs_process_reg_op()
244 		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {  in amdgpu_debugfs_process_reg_op()
679  * amdgpu_debugfs_gca_config_read - Read from gfx config data
709 	config[no_regs++] = adev->gfx.config.max_shader_engines;  in amdgpu_debugfs_gca_config_read()
710 	config[no_regs++] = adev->gfx.config.max_tile_pipes;  in amdgpu_debugfs_gca_config_read()
711 	config[no_regs++] = adev->gfx.config.max_cu_per_sh;  in amdgpu_debugfs_gca_config_read()
712 	config[no_regs++] = adev->gfx.config.max_sh_per_se;  in amdgpu_debugfs_gca_config_read()
713 	config[no_regs++] = adev->gfx.config.max_backends_per_se;  in amdgpu_debugfs_gca_config_read()
714 	config[no_regs++] = adev->gfx.config.max_texture_channel_caches;  in amdgpu_debugfs_gca_config_read()
715 	config[no_regs++] = adev->gfx.config.max_gprs;  in amdgpu_debugfs_gca_config_read()
716 	config[no_regs++] = adev->gfx.config.max_gs_threads;  in amdgpu_debugfs_gca_config_read()
717 	config[no_regs++] = adev->gfx.config.max_hw_contexts;  in amdgpu_debugfs_gca_config_read()
718 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;  in amdgpu_debugfs_gca_config_read()
719 	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;  in amdgpu_debugfs_gca_config_read()
720 	config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
721 	config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;  in amdgpu_debugfs_gca_config_read()
722 	config[no_regs++] = adev->gfx.config.num_tile_pipes;  in amdgpu_debugfs_gca_config_read()
723 	config[no_regs++] = adev->gfx.config.backend_enable_mask;  in amdgpu_debugfs_gca_config_read()
724 	config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;  in amdgpu_debugfs_gca_config_read()
725 	config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;  in amdgpu_debugfs_gca_config_read()
726 	config[no_regs++] = adev->gfx.config.shader_engine_tile_size;  in amdgpu_debugfs_gca_config_read()
727 	config[no_regs++] = adev->gfx.config.num_gpus;  in amdgpu_debugfs_gca_config_read()
728 	config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;  in amdgpu_debugfs_gca_config_read()
729 	config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;  in amdgpu_debugfs_gca_config_read()
730 	config[no_regs++] = adev->gfx.config.gb_addr_config;  in amdgpu_debugfs_gca_config_read()
731 	config[no_regs++] = adev->gfx.config.num_rbs;  in amdgpu_debugfs_gca_config_read()
859  * Followed by WAVE STATUS registers relevant to the GFX IP version
898 	if (adev->gfx.funcs->read_wave_data)  in amdgpu_debugfs_wave_read()
899 		adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);  in amdgpu_debugfs_wave_read()
992 		if (adev->gfx.funcs->read_wave_vgprs)  in amdgpu_debugfs_gpr_read()
993 			adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);  in amdgpu_debugfs_gpr_read()
995 		if (adev->gfx.funcs->read_wave_sgprs)  in amdgpu_debugfs_gpr_read()
996 			adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);  in amdgpu_debugfs_gpr_read()