Lines Matching full:gfx
831 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
932 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
933 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
934 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
935 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
936 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
937 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
938 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
939 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
940 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
941 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
944 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_free_microcode()
945 adev->gfx.mec2_fw = NULL; in gfx_v8_0_free_microcode()
947 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
997 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1000 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1004 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1008 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1011 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
1012 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1013 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1017 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1020 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1024 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1028 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1031 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
1032 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1034 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1038 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1041 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1045 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1049 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1052 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
1053 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1054 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1060 if (adev->gfx.ce_feature_version >= 46 && in gfx_v8_0_init_microcode()
1061 adev->gfx.pfp_feature_version >= 46) { in gfx_v8_0_init_microcode()
1068 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1071 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1072 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
1073 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1074 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1076 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1078 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1080 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1082 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1084 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1086 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1088 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1090 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1092 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
1095 adev->gfx.rlc.register_list_format = in gfx_v8_0_init_microcode()
1096 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v8_0_init_microcode()
1097 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v8_0_init_microcode()
1099 if (!adev->gfx.rlc.register_list_format) { in gfx_v8_0_init_microcode()
1106 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1107 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1109 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v8_0_init_microcode()
1113 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v8_0_init_microcode()
1114 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v8_0_init_microcode()
1118 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1121 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1125 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1129 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1132 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1133 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
1134 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
1140 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1143 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1147 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
1150 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1154 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
1155 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
1157 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
1161 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1167 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
1174 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
1181 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
1188 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
1195 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1201 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
1208 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
1213 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
1216 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
1227 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
1228 adev->gfx.pfp_fw = NULL; in gfx_v8_0_init_microcode()
1229 release_firmware(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
1230 adev->gfx.me_fw = NULL; in gfx_v8_0_init_microcode()
1231 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
1232 adev->gfx.ce_fw = NULL; in gfx_v8_0_init_microcode()
1233 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
1234 adev->gfx.rlc_fw = NULL; in gfx_v8_0_init_microcode()
1235 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
1236 adev->gfx.mec_fw = NULL; in gfx_v8_0_init_microcode()
1237 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
1238 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
1250 if (adev->gfx.rlc.cs_data == NULL) in gfx_v8_0_get_csb_buffer()
1262 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v8_0_get_csb_buffer()
1280 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_get_csb_buffer()
1281 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_get_csb_buffer()
1303 adev->gfx.rlc.cs_data = vi_cs_data; in gfx_v8_0_rlc_init()
1305 cs_data = adev->gfx.rlc.cs_data; in gfx_v8_0_rlc_init()
1316 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v8_0_rlc_init()
1323 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v8_0_rlc_init()
1324 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v8_0_rlc_init()
1331 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v8_0_mec_fini()
1340 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v8_0_mec_init()
1345 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()
1349 &adev->gfx.mec.hpd_eop_obj, in gfx_v8_0_mec_init()
1350 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v8_0_mec_init()
1359 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1360 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
1522 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v8_0_do_edc_gpr_workarounds()
1694 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1695 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1696 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1697 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1698 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1699 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1700 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1701 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1702 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1704 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1705 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1706 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1707 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1711 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1712 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
1713 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
1714 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1715 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
1716 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
1717 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1718 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1719 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1721 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1722 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1723 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1724 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1732 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1733 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1734 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1736 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1737 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1738 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1739 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1747 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1748 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1749 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1751 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1752 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1753 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1754 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1759 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1760 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1761 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1763 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1764 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1765 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1766 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1768 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1769 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1770 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1771 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1776 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1777 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1778 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1779 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1781 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1782 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1783 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1785 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1786 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1787 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1788 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1792 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1793 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1795 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1796 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1797 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1798 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1799 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1800 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1802 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1803 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1804 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1805 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1809 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1810 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1811 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1812 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1813 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1814 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1815 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1816 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1817 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1819 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1820 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1821 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1822 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1827 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1828 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1830 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1832 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1835 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1836 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1860 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1862 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1865 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1866 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1867 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1870 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1871 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1872 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1875 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1887 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1897 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1900 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v8_0_compute_ring_init()
1910 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v8_0_compute_ring_init()
1915 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v8_0_compute_ring_init()
1922 &adev->gfx.eop_irq, irq_type, hw_prio); in gfx_v8_0_compute_ring_init()
1947 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1952 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
1956 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v8_0_sw_init()
1957 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v8_0_sw_init()
1960 …q_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1966 &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1972 &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1978 &adev->gfx.cp_ecc_error_irq); in gfx_v8_0_sw_init()
1984 &adev->gfx.sq_irq); in gfx_v8_0_sw_init()
1990 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); in gfx_v8_0_sw_init()
1992 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
1998 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v8_0_sw_init()
2002 r = adev->gfx.rlc.funcs->init(adev); in gfx_v8_0_sw_init()
2014 /* set up the gfx ring */ in gfx_v8_0_sw_init()
2015 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
2016 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
2018 sprintf(ring->name, "gfx"); in gfx_v8_0_sw_init()
2019 /* no gfx doorbells on iceland */ in gfx_v8_0_sw_init()
2025 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, in gfx_v8_0_sw_init()
2035 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
2036 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v8_0_sw_init()
2037 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v8_0_sw_init()
2058 kiq = &adev->gfx.kiq; in gfx_v8_0_sw_init()
2068 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
2082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
2083 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
2084 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
2085 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
2088 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v8_0_sw_fini()
2093 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v8_0_sw_fini()
2094 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
2095 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v8_0_sw_fini()
2098 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v8_0_sw_fini()
2099 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v8_0_sw_fini()
2100 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v8_0_sw_fini()
2110 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2111 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); in gfx_v8_0_tiling_mode_table_init()
2114 modearray = adev->gfx.config.tile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2115 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
3468 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()
3469 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3520 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3521 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
3630 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()
3631 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3635 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3636 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3639 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v8_0_setup_rb()
3645 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v8_0_setup_rb()
3646 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v8_0_setup_rb()
3648 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
3649 adev->gfx.config.max_shader_engines, 16); in gfx_v8_0_setup_rb()
3653 if (!adev->gfx.config.backend_enable_mask || in gfx_v8_0_setup_rb()
3654 adev->gfx.config.num_rbs >= num_rb_pipes) { in gfx_v8_0_setup_rb()
3659 adev->gfx.config.backend_enable_mask, in gfx_v8_0_setup_rb()
3664 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_setup_rb()
3665 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3667 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v8_0_setup_rb()
3669 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v8_0_setup_rb()
3671 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v8_0_setup_rb()
3673 adev->gfx.config.rb_config[i][j].raster_config_1 = in gfx_v8_0_setup_rb()
3738 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v8_0_init_gds_vmid()
3755 adev->gfx.config.double_offchip_lds_buf = 1; in gfx_v8_0_config_init()
3759 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v8_0_config_init()
3770 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3771 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3772 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_constants_init()
3827 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_constants_init()
3829 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_constants_init()
3831 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_constants_init()
3833 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_constants_init()
3853 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
3854 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
3900 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v8_0_init_csb()
3903 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3905 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
3907 adev->gfx.rlc.clear_state_size); in gfx_v8_0_init_csb()
3970 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v8_0_init_save_restore_list()
3971 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v8_0_init_save_restore_list()
3977 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v8_0_init_save_restore_list()
3989 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3990 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()
3993 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); in gfx_v8_0_init_save_restore_list()
3994 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) in gfx_v8_0_init_save_restore_list()
3997 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v8_0_init_save_restore_list()
3999 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); in gfx_v8_0_init_save_restore_list()
4004 adev->gfx.rlc.starting_offsets_start); in gfx_v8_0_init_save_restore_list()
4069 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v8_0_init_pg()
4071 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v8_0_init_pg()
4118 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_rlc_resume()
4119 adev->gfx.rlc.funcs->reset(adev); in gfx_v8_0_rlc_resume()
4121 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_rlc_resume()
4174 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
4180 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
4216 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v8_0_cp_gfx_start()
4217 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v8_0_cp_gfx_start()
4238 /* no gfx doorbells on iceland */ in gfx_v8_0_set_cpg_door_bell()
4283 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
4329 adev->gfx.kiq.ring.sched.ready = false; in gfx_v8_0_cp_compute_enable()
4351 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable()
4356 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v8_0_kiq_kcq_enable()
4370 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4384 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()
4385 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kiq_kcq_enable()
4638 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4639 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4660 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kiq_init_queue()
4661 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kiq_init_queue()
4671 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v8_0_kcq_init_queue()
4683 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4684 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4687 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v8_0_kcq_init_queue()
4688 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); in gfx_v8_0_kcq_init_queue()
4713 ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_resume()
4738 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()
4739 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_resume()
4770 /* collect all the ring_tests here, gfx, kiq, compute */ in gfx_v8_0_cp_test_all_rings()
4771 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_test_all_rings()
4776 ring = &adev->gfx.kiq.ring; in gfx_v8_0_cp_test_all_rings()
4781 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()
4782 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_test_all_rings()
4831 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v8_0_hw_init()
4843 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kcq_disable()
4845 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()
4849 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()
4850 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_kcq_disable()
4923 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_hw_fini()
4924 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_hw_fini()
4926 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_hw_fini()
4928 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_hw_fini()
4943 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_hw_fini()
5013 adev->gfx.grbm_soft_reset = grbm_soft_reset; in gfx_v8_0_check_soft_reset()
5014 adev->gfx.srbm_soft_reset = srbm_soft_reset; in gfx_v8_0_check_soft_reset()
5017 adev->gfx.grbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5018 adev->gfx.srbm_soft_reset = 0; in gfx_v8_0_check_soft_reset()
5028 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_pre_soft_reset()
5029 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_pre_soft_reset()
5032 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_pre_soft_reset()
5035 adev->gfx.rlc.funcs->stop(adev); in gfx_v8_0_pre_soft_reset()
5039 /* Disable GFX parsing/prefetching */ in gfx_v8_0_pre_soft_reset()
5048 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()
5049 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_pre_soft_reset()
5070 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_soft_reset()
5071 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_soft_reset()
5074 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_soft_reset()
5075 srbm_soft_reset = adev->gfx.srbm_soft_reset; in gfx_v8_0_soft_reset()
5131 if ((!adev->gfx.grbm_soft_reset) && in gfx_v8_0_post_soft_reset()
5132 (!adev->gfx.srbm_soft_reset)) in gfx_v8_0_post_soft_reset()
5135 grbm_soft_reset = adev->gfx.grbm_soft_reset; in gfx_v8_0_post_soft_reset()
5143 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()
5144 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_post_soft_reset()
5162 adev->gfx.rlc.funcs->start(adev); in gfx_v8_0_post_soft_reset()
5179 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5183 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
5297 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
5298 adev->gfx.num_compute_rings = amdgpu_num_kcq; in gfx_v8_0_early_init()
5299 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; in gfx_v8_0_early_init()
5313 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v8_0_late_init()
5317 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v8_0_late_init()
5326 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v8_0_late_init()
5332 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0); in gfx_v8_0_late_init()
5378 /* Read any GFX register to wake up GFX. */ in cz_enable_gfx_pipeline_power_gating()
5800 /* disable cntx_empty_int_enable & GFX Idle interrupt */ in gfx_v8_0_update_coarse_grain_clock_gating()
5810 /* read gfx register to wake up cgcg */ in gfx_v8_0_update_coarse_grain_clock_gating()
6337 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v8_ring_emit_cntxcntl()
6641 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
6645 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
6646 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
6671 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v8_0_fault()
6675 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()
6676 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_fault()
6784 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work); in gfx_v8_0_sq_irq_work_func()
6801 if (work_pending(&adev->gfx.sq_work.work)) { in gfx_v8_0_sq_irq()
6804 adev->gfx.sq_work.ih_data = ih_data; in gfx_v8_0_sq_irq()
6805 schedule_work(&adev->gfx.sq_work.work); in gfx_v8_0_sq_irq()
6966 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; in gfx_v8_0_set_ring_funcs()
6968 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
6969 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
6971 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
6972 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
7002 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7003 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
7005 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7006 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
7008 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7009 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
7011 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7012 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; in gfx_v8_0_set_irq_funcs()
7014 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7015 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs; in gfx_v8_0_set_irq_funcs()
7020 adev->gfx.rlc.funcs = &iceland_rlc_funcs; in gfx_v8_0_set_rlc_funcs()
7053 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()
7062 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v8_0_get_cu_info()
7071 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()
7076 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
7077 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
7088 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()