Lines Matching full:gfx
341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
363 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
366 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v6_0_init_microcode()
369 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_init_microcode()
370 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
371 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
374 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
377 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v6_0_init_microcode()
378 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()
379 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
380 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
385 release_firmware(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
386 adev->gfx.pfp_fw = NULL; in gfx_v6_0_init_microcode()
387 release_firmware(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
388 adev->gfx.me_fw = NULL; in gfx_v6_0_init_microcode()
389 release_firmware(adev->gfx.ce_fw); in gfx_v6_0_init_microcode()
390 adev->gfx.ce_fw = NULL; in gfx_v6_0_init_microcode()
391 release_firmware(adev->gfx.rlc_fw); in gfx_v6_0_init_microcode()
392 adev->gfx.rlc_fw = NULL; in gfx_v6_0_init_microcode()
399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init()
402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); in gfx_v6_0_tiling_mode_table_init()
403 tilemode = adev->gfx.config.tile_mode_array; in gfx_v6_0_tiling_mode_table_init()
405 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v6_0_tiling_mode_table_init()
1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()
1336 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1377 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()
1378 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v6_0_write_harvested_raster_configs()
1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()
1470 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1479 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1485 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v6_0_setup_rb()
1486 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v6_0_setup_rb()
1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()
1489 adev->gfx.config.max_shader_engines, 16); in gfx_v6_0_setup_rb()
1493 if (!adev->gfx.config.backend_enable_mask || in gfx_v6_0_setup_rb()
1494 adev->gfx.config.num_rbs >= num_rb_pipes) in gfx_v6_0_setup_rb()
1498 adev->gfx.config.backend_enable_mask, in gfx_v6_0_setup_rb()
1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_rb()
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1505 adev->gfx.config.rb_config[i][j].rb_backend_disable = in gfx_v6_0_setup_rb()
1507 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = in gfx_v6_0_setup_rb()
1509 adev->gfx.config.rb_config[i][j].raster_config = in gfx_v6_0_setup_rb()
1538 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v6_0_get_cu_enabled()
1550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_setup_spi()
1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1573 adev->gfx.config.double_offchip_lds_buf = 0; in gfx_v6_0_config_init()
1586 adev->gfx.config.max_shader_engines = 2; in gfx_v6_0_constants_init()
1587 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()
1588 adev->gfx.config.max_cu_per_sh = 8; in gfx_v6_0_constants_init()
1589 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1590 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1591 adev->gfx.config.max_texture_channel_caches = 12; in gfx_v6_0_constants_init()
1592 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1593 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1594 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1596 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1597 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1598 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1599 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1603 adev->gfx.config.max_shader_engines = 2; in gfx_v6_0_constants_init()
1604 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()
1605 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1606 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1607 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1608 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v6_0_constants_init()
1609 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1610 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1611 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1613 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1614 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v6_0_constants_init()
1615 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1616 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1620 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1621 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1622 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1623 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1624 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()
1625 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v6_0_constants_init()
1626 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1627 adev->gfx.config.max_gs_threads = 32; in gfx_v6_0_constants_init()
1628 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1630 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1631 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1632 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1633 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1637 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1638 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1639 adev->gfx.config.max_cu_per_sh = 6; in gfx_v6_0_constants_init()
1640 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
1641 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()
1642 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v6_0_constants_init()
1643 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1644 adev->gfx.config.max_gs_threads = 16; in gfx_v6_0_constants_init()
1645 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1647 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1648 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1649 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1650 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1654 adev->gfx.config.max_shader_engines = 1; in gfx_v6_0_constants_init()
1655 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()
1656 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()
1657 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
1658 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
1659 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v6_0_constants_init()
1660 adev->gfx.config.max_gprs = 256; in gfx_v6_0_constants_init()
1661 adev->gfx.config.max_gs_threads = 16; in gfx_v6_0_constants_init()
1662 adev->gfx.config.max_hw_contexts = 8; in gfx_v6_0_constants_init()
1664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v6_0_constants_init()
1665 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; in gfx_v6_0_constants_init()
1666 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v6_0_constants_init()
1667 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v6_0_constants_init()
1681 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v6_0_constants_init()
1682 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v6_0_constants_init()
1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
1685 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v6_0_constants_init()
1687 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v6_0_constants_init()
1688 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v6_0_constants_init()
1689 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v6_0_constants_init()
1690 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v6_0_constants_init()
1691 adev->gfx.config.num_gpus = 1; in gfx_v6_0_constants_init()
1692 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v6_0_constants_init()
1695 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v6_0_constants_init()
1708 if (adev->gfx.config.max_shader_engines == 2) in gfx_v6_0_constants_init()
1710 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v6_0_constants_init()
1745 …WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRO… in gfx_v6_0_constants_init()
1746 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v6_0_constants_init()
1747 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v6_0_constants_init()
1748 … (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v6_0_constants_init()
1784 adev->gfx.scratch.num_reg = 8; in gfx_v6_0_scratch_init()
1785 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v6_0_scratch_init()
1786 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v6_0_scratch_init()
1898 * Allocate an IB and execute it on the gfx ring (SI).
1899 * Provides a basic gfx ring test to verify that IBs are working.
1974 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v6_0_cp_gfx_load_microcode()
1978 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1979 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1980 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_cp_gfx_load_microcode()
1988 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
1997 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
2006 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()
2024 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_start()
2035 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); in gfx_v6_0_cp_gfx_start()
2057 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2102 /* ring 0 - compute and gfx */ in gfx_v6_0_cp_gfx_resume()
2104 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_cp_gfx_resume()
2148 if (ring == &adev->gfx.gfx_ring[0]) in gfx_v6_0_ring_get_wptr()
2150 else if (ring == &adev->gfx.compute_ring[0]) in gfx_v6_0_ring_get_wptr()
2152 else if (ring == &adev->gfx.compute_ring[1]) in gfx_v6_0_ring_get_wptr()
2170 if (ring == &adev->gfx.compute_ring[0]) { in gfx_v6_0_ring_set_wptr_compute()
2173 } else if (ring == &adev->gfx.compute_ring[1]) { in gfx_v6_0_ring_set_wptr_compute()
2193 ring = &adev->gfx.compute_ring[0]; in gfx_v6_0_cp_compute_resume()
2213 ring = &adev->gfx.compute_ring[1]; in gfx_v6_0_cp_compute_resume()
2234 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); in gfx_v6_0_cp_compute_resume()
2268 /* read a gfx register */ in gfx_v6_0_enable_gui_idle_interrupt()
2379 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2380 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2383 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2384 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2385 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2386 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2397 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2398 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2402 &adev->gfx.rlc.clear_state_obj, in gfx_v6_0_rlc_init()
2403 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2404 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v6_0_rlc_init()
2412 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v6_0_rlc_init()
2413 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2416 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); in gfx_v6_0_rlc_init()
2418 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2419 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2525 if (!adev->gfx.rlc_fw) in gfx_v6_0_rlc_resume()
2528 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_rlc_resume()
2529 adev->gfx.rlc.funcs->reset(adev); in gfx_v6_0_rlc_resume()
2543 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_rlc_resume()
2546 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_rlc_resume()
2557 adev->gfx.rlc.funcs->start(adev); in gfx_v6_0_rlc_resume()
2710 if (adev->gfx.rlc.cp_table_ptr == NULL)
2713 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2717 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2719 (adev->gfx.ce_fw->data +
2725 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2727 (adev->gfx.pfp_fw->data +
2733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2735 (adev->gfx.me_fw->data +
2741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2743 (adev->gfx.mec_fw->data +
2749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2751 (adev->gfx.mec2_fw->data +
2783 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); in gfx_v6_0_init_ao_cu_mask()
2787 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); in gfx_v6_0_init_ao_cu_mask()
2823 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2825 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2847 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_size()
2855 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_size()
2880 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_buffer()
2891 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_buffer()
2907 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v6_0_get_csb_buffer()
2931 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2932 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2939 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2940 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2964 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v6_0_get_gpu_clock_counter()
2968 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v6_0_get_gpu_clock_counter()
3066 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; in gfx_v6_0_early_init()
3067 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; in gfx_v6_0_early_init()
3068 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; in gfx_v6_0_early_init()
3069 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; in gfx_v6_0_early_init()
3082 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); in gfx_v6_0_sw_init()
3086 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); in gfx_v6_0_sw_init()
3090 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); in gfx_v6_0_sw_init()
3098 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v6_0_sw_init()
3102 r = adev->gfx.rlc.funcs->init(adev); in gfx_v6_0_sw_init()
3108 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v6_0_sw_init()
3109 ring = &adev->gfx.gfx_ring[i]; in gfx_v6_0_sw_init()
3111 sprintf(ring->name, "gfx"); in gfx_v6_0_sw_init()
3113 &adev->gfx.eop_irq, in gfx_v6_0_sw_init()
3120 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()
3127 ring = &adev->gfx.compute_ring[i]; in gfx_v6_0_sw_init()
3137 &adev->gfx.eop_irq, irq_type, in gfx_v6_0_sw_init()
3151 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_sw_fini()
3152 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v6_0_sw_fini()
3153 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()
3154 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v6_0_sw_fini()
3168 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v6_0_hw_init()
3176 adev->gfx.ce_ram_size = 0x8000; in gfx_v6_0_hw_init()
3186 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_hw_fini()
3372 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v6_0_eop_irq()
3376 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); in gfx_v6_0_eop_irq()
3391 ring = &adev->gfx.gfx_ring[0]; in gfx_v6_0_fault()
3395 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; in gfx_v6_0_fault()
3554 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v6_0_set_ring_funcs()
3555 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; in gfx_v6_0_set_ring_funcs()
3556 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
3557 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; in gfx_v6_0_set_ring_funcs()
3577 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v6_0_set_irq_funcs()
3578 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; in gfx_v6_0_set_irq_funcs()
3580 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v6_0_set_irq_funcs()
3581 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; in gfx_v6_0_set_irq_funcs()
3583 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v6_0_set_irq_funcs()
3584 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; in gfx_v6_0_set_irq_funcs()
3591 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v6_0_get_cu_info()
3598 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v6_0_get_cu_info()
3605 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v6_0_get_cu_info()
3606 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_get_cu_info()
3617 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()