1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "amdgpu_gfx.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_si.h"
31 #include "bif/bif_3_0_d.h"
32 #include "bif/bif_3_0_sh_mask.h"
33 #include "oss/oss_1_0_d.h"
34 #include "oss/oss_1_0_sh_mask.h"
35 #include "gca/gfx_6_0_d.h"
36 #include "gca/gfx_6_0_sh_mask.h"
37 #include "gmc/gmc_6_0_d.h"
38 #include "gmc/gmc_6_0_sh_mask.h"
39 #include "dce/dce_6_0_d.h"
40 #include "dce/dce_6_0_sh_mask.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "si_enums.h"
43 #include "si.h"
44
45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
48
49 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
50 MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
51 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
52 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
53
54 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
55 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
56 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
57 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
58
59 MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
60 MODULE_FIRMWARE("amdgpu/verde_me.bin");
61 MODULE_FIRMWARE("amdgpu/verde_ce.bin");
62 MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
63
64 MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
65 MODULE_FIRMWARE("amdgpu/oland_me.bin");
66 MODULE_FIRMWARE("amdgpu/oland_ce.bin");
67 MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
68
69 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
70 MODULE_FIRMWARE("amdgpu/hainan_me.bin");
71 MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
72 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
73
74 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
75 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
76 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
77 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
78
79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
80 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
81 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
82 #define MICRO_TILE_MODE(x) ((x) << 0)
83 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
84 #define BANK_WIDTH(x) ((x) << 14)
85 #define BANK_HEIGHT(x) ((x) << 16)
86 #define MACRO_TILE_ASPECT(x) ((x) << 18)
87 #define NUM_BANKS(x) ((x) << 20)
88
89 static const u32 verde_rlc_save_restore_register_list[] =
90 {
91 (0x8000 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8040 << 16) | (0x98f4 >> 2),
94 0x00000000,
95 (0x8000 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8040 << 16) | (0xe80 >> 2),
98 0x00000000,
99 (0x8000 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8040 << 16) | (0x89bc >> 2),
102 0x00000000,
103 (0x8000 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x8040 << 16) | (0x8c1c >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0x98f0 >> 2),
108 0x00000000,
109 (0x9c00 << 16) | (0xe7c >> 2),
110 0x00000000,
111 (0x8000 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x8040 << 16) | (0x9148 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9150 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x897c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x8d8c >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0xac54 >> 2),
122 0X00000000,
123 0x3,
124 (0x9c00 << 16) | (0x98f8 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9910 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9914 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x9918 >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x991c >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9920 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9924 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x9928 >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x992c >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9930 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9934 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x9938 >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x993c >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9940 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9944 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x9948 >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x994c >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9950 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9954 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x9958 >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x995c >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9960 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9964 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x9968 >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x996c >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9970 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9974 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x9978 >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x997c >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9980 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9984 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x9988 >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x998c >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c00 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c14 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c04 >> 2),
195 0x00000000,
196 (0x9c00 << 16) | (0x8c08 >> 2),
197 0x00000000,
198 (0x8000 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8040 << 16) | (0x9b7c >> 2),
201 0x00000000,
202 (0x8000 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8040 << 16) | (0xe84 >> 2),
205 0x00000000,
206 (0x8000 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8040 << 16) | (0x89c0 >> 2),
209 0x00000000,
210 (0x8000 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8040 << 16) | (0x914c >> 2),
213 0x00000000,
214 (0x8000 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8040 << 16) | (0x8c20 >> 2),
217 0x00000000,
218 (0x8000 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x8040 << 16) | (0x9354 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9060 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9364 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x9100 >> 2),
227 0x00000000,
228 (0x9c00 << 16) | (0x913c >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e0 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e4 >> 2),
233 0x00000000,
234 (0x8000 << 16) | (0x90e8 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e0 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e4 >> 2),
239 0x00000000,
240 (0x8040 << 16) | (0x90e8 >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8bcc >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x8b24 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x88c4 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8e50 >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8c0c >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e58 >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x8e5c >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x9508 >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x950c >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0x9494 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac0c >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac10 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xac14 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xae00 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0xac08 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88d4 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88c8 >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x88cc >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x89b0 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8b10 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x8a14 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9830 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9834 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9838 >> 2),
289 0x00000000,
290 (0x9c00 << 16) | (0x9a10 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9870 >> 2),
293 0x00000000,
294 (0x8000 << 16) | (0x9874 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9870 >> 2),
297 0x00000000,
298 (0x8001 << 16) | (0x9874 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9870 >> 2),
301 0x00000000,
302 (0x8040 << 16) | (0x9874 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9870 >> 2),
305 0x00000000,
306 (0x8041 << 16) | (0x9874 >> 2),
307 0x00000000,
308 0x00000000
309 };
310
gfx_v6_0_init_microcode(struct amdgpu_device * adev)311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
312 {
313 const char *chip_name;
314 char fw_name[30];
315 int err;
316 const struct gfx_firmware_header_v1_0 *cp_hdr;
317 const struct rlc_firmware_header_v1_0 *rlc_hdr;
318
319 DRM_DEBUG("\n");
320
321 switch (adev->asic_type) {
322 case CHIP_TAHITI:
323 chip_name = "tahiti";
324 break;
325 case CHIP_PITCAIRN:
326 chip_name = "pitcairn";
327 break;
328 case CHIP_VERDE:
329 chip_name = "verde";
330 break;
331 case CHIP_OLAND:
332 chip_name = "oland";
333 break;
334 case CHIP_HAINAN:
335 chip_name = "hainan";
336 break;
337 default: BUG();
338 }
339
340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
342 if (err)
343 goto out;
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
345 if (err)
346 goto out;
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
350
351 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
353 if (err)
354 goto out;
355 err = amdgpu_ucode_validate(adev->gfx.me_fw);
356 if (err)
357 goto out;
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
361
362 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
363 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
364 if (err)
365 goto out;
366 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
367 if (err)
368 goto out;
369 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
370 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
371 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
372
373 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
374 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
375 if (err)
376 goto out;
377 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
378 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
379 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
380 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
381
382 out:
383 if (err) {
384 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
385 release_firmware(adev->gfx.pfp_fw);
386 adev->gfx.pfp_fw = NULL;
387 release_firmware(adev->gfx.me_fw);
388 adev->gfx.me_fw = NULL;
389 release_firmware(adev->gfx.ce_fw);
390 adev->gfx.ce_fw = NULL;
391 release_firmware(adev->gfx.rlc_fw);
392 adev->gfx.rlc_fw = NULL;
393 }
394 return err;
395 }
396
gfx_v6_0_tiling_mode_table_init(struct amdgpu_device * adev)397 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
398 {
399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
400 u32 reg_offset, split_equal_to_row_size, *tilemode;
401
402 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
403 tilemode = adev->gfx.config.tile_mode_array;
404
405 switch (adev->gfx.config.mem_row_size_in_kb) {
406 case 1:
407 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
408 break;
409 case 2:
410 default:
411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
412 break;
413 case 4:
414 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
415 break;
416 }
417
418 if (adev->asic_type == CHIP_VERDE) {
419 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
420 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
421 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
426 NUM_BANKS(ADDR_SURF_16_BANK);
427 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
428 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
429 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
430 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
434 NUM_BANKS(ADDR_SURF_16_BANK);
435 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
436 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
437 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
438 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
439 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
440 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
441 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
442 NUM_BANKS(ADDR_SURF_16_BANK);
443 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
444 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
445 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
449 NUM_BANKS(ADDR_SURF_8_BANK) |
450 TILE_SPLIT(split_equal_to_row_size);
451 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
452 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
453 PIPE_CONFIG(ADDR_SURF_P4_8x16);
454 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
455 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
456 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
457 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
458 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
460 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
461 NUM_BANKS(ADDR_SURF_4_BANK);
462 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
463 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
464 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
465 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
469 NUM_BANKS(ADDR_SURF_4_BANK);
470 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
471 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
472 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
473 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
474 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
477 NUM_BANKS(ADDR_SURF_2_BANK);
478 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
479 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
480 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
481 PIPE_CONFIG(ADDR_SURF_P4_8x16);
482 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
483 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
484 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
485 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
489 NUM_BANKS(ADDR_SURF_16_BANK);
490 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
491 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
492 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
493 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
494 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
495 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
496 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
497 NUM_BANKS(ADDR_SURF_16_BANK);
498 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
499 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
500 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
502 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
505 NUM_BANKS(ADDR_SURF_16_BANK);
506 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
507 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
508 PIPE_CONFIG(ADDR_SURF_P4_8x16);
509 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
510 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
511 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
516 NUM_BANKS(ADDR_SURF_16_BANK);
517 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
518 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
519 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
524 NUM_BANKS(ADDR_SURF_16_BANK);
525 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
526 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
527 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
528 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
532 NUM_BANKS(ADDR_SURF_16_BANK);
533 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
534 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
535 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
536 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
539 NUM_BANKS(ADDR_SURF_16_BANK) |
540 TILE_SPLIT(split_equal_to_row_size);
541 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
542 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
543 PIPE_CONFIG(ADDR_SURF_P4_8x16);
544 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
545 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
546 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
550 NUM_BANKS(ADDR_SURF_16_BANK) |
551 TILE_SPLIT(split_equal_to_row_size);
552 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
553 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
554 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
555 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
558 NUM_BANKS(ADDR_SURF_16_BANK) |
559 TILE_SPLIT(split_equal_to_row_size);
560 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
561 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
562 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
563 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
564 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
565 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
566 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
567 NUM_BANKS(ADDR_SURF_8_BANK);
568 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
569 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
570 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
571 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
572 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
573 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
574 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
575 NUM_BANKS(ADDR_SURF_8_BANK);
576 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
578 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
579 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
580 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
583 NUM_BANKS(ADDR_SURF_4_BANK);
584 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
585 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
586 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
587 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
591 NUM_BANKS(ADDR_SURF_4_BANK);
592 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
593 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
594 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
595 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
596 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
599 NUM_BANKS(ADDR_SURF_2_BANK);
600 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
601 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
602 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
603 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
604 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
607 NUM_BANKS(ADDR_SURF_2_BANK);
608 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
609 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
610 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
611 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
612 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
615 NUM_BANKS(ADDR_SURF_2_BANK);
616 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
617 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
618 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
619 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
620 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
623 NUM_BANKS(ADDR_SURF_2_BANK);
624 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
625 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
626 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
627 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
628 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
631 NUM_BANKS(ADDR_SURF_2_BANK);
632 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
633 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
634 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
635 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
636 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
637 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
638 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
639 NUM_BANKS(ADDR_SURF_2_BANK);
640 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
641 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
642 } else if (adev->asic_type == CHIP_OLAND) {
643 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
644 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
645 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
646 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
647 NUM_BANKS(ADDR_SURF_16_BANK) |
648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
649 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
651 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
653 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
655 NUM_BANKS(ADDR_SURF_16_BANK) |
656 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
657 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
658 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
659 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
660 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
661 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
662 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
663 NUM_BANKS(ADDR_SURF_16_BANK) |
664 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
665 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
666 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
667 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
668 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
669 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
670 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
671 NUM_BANKS(ADDR_SURF_16_BANK) |
672 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
673 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
674 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
675 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
676 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
677 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
679 NUM_BANKS(ADDR_SURF_16_BANK) |
680 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
681 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
683 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
684 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
685 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
686 TILE_SPLIT(split_equal_to_row_size) |
687 NUM_BANKS(ADDR_SURF_16_BANK) |
688 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
691 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
694 TILE_SPLIT(split_equal_to_row_size) |
695 NUM_BANKS(ADDR_SURF_16_BANK) |
696 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
698 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
699 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
700 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
701 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
702 TILE_SPLIT(split_equal_to_row_size) |
703 NUM_BANKS(ADDR_SURF_16_BANK) |
704 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
705 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
706 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
707 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
708 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
709 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
710 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
711 NUM_BANKS(ADDR_SURF_16_BANK) |
712 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
715 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
716 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
717 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
719 NUM_BANKS(ADDR_SURF_16_BANK) |
720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
723 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
724 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
725 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
726 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
727 NUM_BANKS(ADDR_SURF_16_BANK) |
728 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
729 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
730 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
731 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
732 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
733 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
735 NUM_BANKS(ADDR_SURF_16_BANK) |
736 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
739 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
740 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
741 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
742 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
743 NUM_BANKS(ADDR_SURF_16_BANK) |
744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
747 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
748 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
749 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
750 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
751 NUM_BANKS(ADDR_SURF_16_BANK) |
752 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
753 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
754 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
755 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
756 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
757 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
758 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
759 NUM_BANKS(ADDR_SURF_16_BANK) |
760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
763 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
764 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
765 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
766 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
767 NUM_BANKS(ADDR_SURF_16_BANK) |
768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
771 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
772 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
773 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
774 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
775 NUM_BANKS(ADDR_SURF_16_BANK) |
776 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
779 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
780 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
781 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
782 TILE_SPLIT(split_equal_to_row_size) |
783 NUM_BANKS(ADDR_SURF_16_BANK) |
784 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
785 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
786 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
787 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
788 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
789 PIPE_CONFIG(ADDR_SURF_P4_8x16);
790 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
791 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
792 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
796 NUM_BANKS(ADDR_SURF_16_BANK) |
797 TILE_SPLIT(split_equal_to_row_size);
798 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
799 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
800 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
801 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 TILE_SPLIT(split_equal_to_row_size);
806 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
807 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
808 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
809 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
810 NUM_BANKS(ADDR_SURF_16_BANK) |
811 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
812 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
813 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
814 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
815 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
816 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
818 NUM_BANKS(ADDR_SURF_16_BANK) |
819 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
820 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
821 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
822 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
823 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
824 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
825 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
826 NUM_BANKS(ADDR_SURF_16_BANK) |
827 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
830 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
831 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
832 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
833 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
834 NUM_BANKS(ADDR_SURF_16_BANK) |
835 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
836 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
837 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
838 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
839 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
840 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
841 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
842 NUM_BANKS(ADDR_SURF_8_BANK) |
843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
846 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
847 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
848 } else if (adev->asic_type == CHIP_HAINAN) {
849 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
850 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
851 PIPE_CONFIG(ADDR_SURF_P2) |
852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
856 NUM_BANKS(ADDR_SURF_16_BANK);
857 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
858 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
859 PIPE_CONFIG(ADDR_SURF_P2) |
860 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
864 NUM_BANKS(ADDR_SURF_16_BANK);
865 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
866 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
867 PIPE_CONFIG(ADDR_SURF_P2) |
868 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
869 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
870 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
871 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
872 NUM_BANKS(ADDR_SURF_16_BANK);
873 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
874 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
875 PIPE_CONFIG(ADDR_SURF_P2) |
876 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
877 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
878 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
879 NUM_BANKS(ADDR_SURF_8_BANK) |
880 TILE_SPLIT(split_equal_to_row_size);
881 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
882 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
883 PIPE_CONFIG(ADDR_SURF_P2);
884 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
885 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
886 PIPE_CONFIG(ADDR_SURF_P2) |
887 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
888 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
889 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
890 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
891 NUM_BANKS(ADDR_SURF_8_BANK);
892 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
893 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
894 PIPE_CONFIG(ADDR_SURF_P2) |
895 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
896 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
897 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
898 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
899 NUM_BANKS(ADDR_SURF_8_BANK);
900 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
901 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
902 PIPE_CONFIG(ADDR_SURF_P2) |
903 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
904 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
905 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
906 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
907 NUM_BANKS(ADDR_SURF_4_BANK);
908 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
909 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
910 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
911 PIPE_CONFIG(ADDR_SURF_P2);
912 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
913 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
914 PIPE_CONFIG(ADDR_SURF_P2) |
915 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
916 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
919 NUM_BANKS(ADDR_SURF_16_BANK);
920 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
921 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
922 PIPE_CONFIG(ADDR_SURF_P2) |
923 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
924 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
925 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
926 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
927 NUM_BANKS(ADDR_SURF_16_BANK);
928 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
929 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
930 PIPE_CONFIG(ADDR_SURF_P2) |
931 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
932 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
933 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
934 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
935 NUM_BANKS(ADDR_SURF_16_BANK);
936 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
937 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
938 PIPE_CONFIG(ADDR_SURF_P2);
939 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
940 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
941 PIPE_CONFIG(ADDR_SURF_P2) |
942 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
943 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
944 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
945 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
946 NUM_BANKS(ADDR_SURF_16_BANK);
947 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
948 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
949 PIPE_CONFIG(ADDR_SURF_P2) |
950 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
951 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
952 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
953 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
954 NUM_BANKS(ADDR_SURF_16_BANK);
955 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
956 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
957 PIPE_CONFIG(ADDR_SURF_P2) |
958 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
959 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
960 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
961 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
962 NUM_BANKS(ADDR_SURF_16_BANK);
963 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
964 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
965 PIPE_CONFIG(ADDR_SURF_P2) |
966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
969 NUM_BANKS(ADDR_SURF_16_BANK) |
970 TILE_SPLIT(split_equal_to_row_size);
971 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
972 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
973 PIPE_CONFIG(ADDR_SURF_P2);
974 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
975 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
976 PIPE_CONFIG(ADDR_SURF_P2) |
977 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
978 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
979 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
980 NUM_BANKS(ADDR_SURF_16_BANK) |
981 TILE_SPLIT(split_equal_to_row_size);
982 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
983 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
984 PIPE_CONFIG(ADDR_SURF_P2) |
985 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
986 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
987 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
988 NUM_BANKS(ADDR_SURF_16_BANK) |
989 TILE_SPLIT(split_equal_to_row_size);
990 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
991 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
992 PIPE_CONFIG(ADDR_SURF_P2) |
993 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
994 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
995 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
996 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
997 NUM_BANKS(ADDR_SURF_8_BANK);
998 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
999 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1000 PIPE_CONFIG(ADDR_SURF_P2) |
1001 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1002 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1003 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1004 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1005 NUM_BANKS(ADDR_SURF_8_BANK);
1006 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1007 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1008 PIPE_CONFIG(ADDR_SURF_P2) |
1009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1010 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1013 NUM_BANKS(ADDR_SURF_8_BANK);
1014 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1015 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016 PIPE_CONFIG(ADDR_SURF_P2) |
1017 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1018 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1021 NUM_BANKS(ADDR_SURF_8_BANK);
1022 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1023 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1024 PIPE_CONFIG(ADDR_SURF_P2) |
1025 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1026 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1027 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1028 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1029 NUM_BANKS(ADDR_SURF_4_BANK);
1030 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1031 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032 PIPE_CONFIG(ADDR_SURF_P2) |
1033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1034 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1037 NUM_BANKS(ADDR_SURF_4_BANK);
1038 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1039 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1040 PIPE_CONFIG(ADDR_SURF_P2) |
1041 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1042 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1043 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1044 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1045 NUM_BANKS(ADDR_SURF_4_BANK);
1046 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1047 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1048 PIPE_CONFIG(ADDR_SURF_P2) |
1049 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1053 NUM_BANKS(ADDR_SURF_4_BANK);
1054 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1055 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 PIPE_CONFIG(ADDR_SURF_P2) |
1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1058 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1061 NUM_BANKS(ADDR_SURF_4_BANK);
1062 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1063 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064 PIPE_CONFIG(ADDR_SURF_P2) |
1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1066 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1067 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1068 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1069 NUM_BANKS(ADDR_SURF_4_BANK);
1070 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1071 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1072 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1073 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1074 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1076 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1077 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1078 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1079 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1080 NUM_BANKS(ADDR_SURF_16_BANK);
1081 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1082 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1084 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1085 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1086 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1087 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1088 NUM_BANKS(ADDR_SURF_16_BANK);
1089 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1090 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1092 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1093 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1094 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1095 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1096 NUM_BANKS(ADDR_SURF_16_BANK);
1097 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1098 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1103 NUM_BANKS(ADDR_SURF_4_BANK) |
1104 TILE_SPLIT(split_equal_to_row_size);
1105 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1106 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1108 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1109 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1110 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1115 NUM_BANKS(ADDR_SURF_2_BANK);
1116 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1117 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1119 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1120 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1122 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1123 NUM_BANKS(ADDR_SURF_2_BANK);
1124 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1125 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1126 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1127 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1128 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1131 NUM_BANKS(ADDR_SURF_2_BANK);
1132 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1133 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1134 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1135 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1136 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1137 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1138 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1139 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1140 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1143 NUM_BANKS(ADDR_SURF_16_BANK);
1144 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1145 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1147 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1148 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_16_BANK);
1152 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1153 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1154 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1156 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1159 NUM_BANKS(ADDR_SURF_16_BANK);
1160 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1161 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1162 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1163 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1164 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1166 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1170 NUM_BANKS(ADDR_SURF_16_BANK);
1171 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1172 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1173 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1174 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1175 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1178 NUM_BANKS(ADDR_SURF_16_BANK);
1179 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1180 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1181 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1182 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1183 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1184 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1185 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1186 NUM_BANKS(ADDR_SURF_16_BANK);
1187 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1188 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1189 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193 NUM_BANKS(ADDR_SURF_16_BANK) |
1194 TILE_SPLIT(split_equal_to_row_size);
1195 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1196 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1197 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1198 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1199 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1200 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1201 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1204 NUM_BANKS(ADDR_SURF_16_BANK) |
1205 TILE_SPLIT(split_equal_to_row_size);
1206 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1207 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1208 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1209 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1212 NUM_BANKS(ADDR_SURF_16_BANK) |
1213 TILE_SPLIT(split_equal_to_row_size);
1214 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1215 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1216 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1218 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1221 NUM_BANKS(ADDR_SURF_4_BANK);
1222 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1223 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1224 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1226 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1227 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1228 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1229 NUM_BANKS(ADDR_SURF_4_BANK);
1230 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1231 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1234 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1235 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1236 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1237 NUM_BANKS(ADDR_SURF_2_BANK);
1238 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1239 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1240 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1242 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1243 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1244 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1245 NUM_BANKS(ADDR_SURF_2_BANK);
1246 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1247 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1250 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1253 NUM_BANKS(ADDR_SURF_2_BANK);
1254 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1255 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1258 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1261 NUM_BANKS(ADDR_SURF_2_BANK);
1262 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1263 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1264 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1266 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1269 NUM_BANKS(ADDR_SURF_2_BANK);
1270 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1271 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1273 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1274 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1277 NUM_BANKS(ADDR_SURF_2_BANK);
1278 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1279 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1280 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1281 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1282 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1285 NUM_BANKS(ADDR_SURF_2_BANK);
1286 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1287 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1288 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1289 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1290 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1293 NUM_BANKS(ADDR_SURF_2_BANK);
1294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1295 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1296 } else {
1297 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1298 }
1299 }
1300
gfx_v6_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1302 u32 sh_num, u32 instance)
1303 {
1304 u32 data;
1305
1306 if (instance == 0xffffffff)
1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1308 else
1309 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1310
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1312 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1313 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1314 else if (se_num == 0xffffffff)
1315 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1316 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1317 else if (sh_num == 0xffffffff)
1318 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1320 else
1321 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1323 WREG32(mmGRBM_GFX_INDEX, data);
1324 }
1325
gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device * adev)1326 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1327 {
1328 u32 data, mask;
1329
1330 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1331 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1332
1333 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1334
1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1336 adev->gfx.config.max_sh_per_se);
1337
1338 return ~data & mask;
1339 }
1340
gfx_v6_0_raster_config(struct amdgpu_device * adev,u32 * rconf)1341 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1342 {
1343 switch (adev->asic_type) {
1344 case CHIP_TAHITI:
1345 case CHIP_PITCAIRN:
1346 *rconf |=
1347 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1348 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1349 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1350 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1351 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1352 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1353 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1354 break;
1355 case CHIP_VERDE:
1356 *rconf |=
1357 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1358 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1359 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1360 break;
1361 case CHIP_OLAND:
1362 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1363 break;
1364 case CHIP_HAINAN:
1365 *rconf |= 0x0;
1366 break;
1367 default:
1368 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1369 break;
1370 }
1371 }
1372
gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device * adev,u32 raster_config,unsigned rb_mask,unsigned num_rb)1373 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1374 u32 raster_config, unsigned rb_mask,
1375 unsigned num_rb)
1376 {
1377 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1378 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1379 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1380 unsigned rb_per_se = num_rb / num_se;
1381 unsigned se_mask[4];
1382 unsigned se;
1383
1384 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1385 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1386 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1387 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1388
1389 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1390 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1391 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1392
1393 for (se = 0; se < num_se; se++) {
1394 unsigned raster_config_se = raster_config;
1395 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1396 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1397 int idx = (se / 2) * 2;
1398
1399 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1400 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1401
1402 if (!se_mask[idx])
1403 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1404 else
1405 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1406 }
1407
1408 pkr0_mask &= rb_mask;
1409 pkr1_mask &= rb_mask;
1410 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1411 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1412
1413 if (!pkr0_mask)
1414 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1415 else
1416 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1417 }
1418
1419 if (rb_per_se >= 2) {
1420 unsigned rb0_mask = 1 << (se * rb_per_se);
1421 unsigned rb1_mask = rb0_mask << 1;
1422
1423 rb0_mask &= rb_mask;
1424 rb1_mask &= rb_mask;
1425 if (!rb0_mask || !rb1_mask) {
1426 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1427
1428 if (!rb0_mask)
1429 raster_config_se |=
1430 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1431 else
1432 raster_config_se |=
1433 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1434 }
1435
1436 if (rb_per_se > 2) {
1437 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1438 rb1_mask = rb0_mask << 1;
1439 rb0_mask &= rb_mask;
1440 rb1_mask &= rb_mask;
1441 if (!rb0_mask || !rb1_mask) {
1442 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1443
1444 if (!rb0_mask)
1445 raster_config_se |=
1446 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1447 else
1448 raster_config_se |=
1449 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1450 }
1451 }
1452 }
1453
1454 /* GRBM_GFX_INDEX has a different offset on SI */
1455 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1456 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1457 }
1458
1459 /* GRBM_GFX_INDEX has a different offset on SI */
1460 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1461 }
1462
gfx_v6_0_setup_rb(struct amdgpu_device * adev)1463 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1464 {
1465 int i, j;
1466 u32 data;
1467 u32 raster_config = 0;
1468 u32 active_rbs = 0;
1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1470 adev->gfx.config.max_sh_per_se;
1471 unsigned num_rb_pipes;
1472
1473 mutex_lock(&adev->grbm_idx_mutex);
1474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1476 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1477 data = gfx_v6_0_get_rb_active_bitmap(adev);
1478 active_rbs |= data <<
1479 ((i * adev->gfx.config.max_sh_per_se + j) *
1480 rb_bitmap_width_per_sh);
1481 }
1482 }
1483 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1484
1485 adev->gfx.config.backend_enable_mask = active_rbs;
1486 adev->gfx.config.num_rbs = hweight32(active_rbs);
1487
1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1489 adev->gfx.config.max_shader_engines, 16);
1490
1491 gfx_v6_0_raster_config(adev, &raster_config);
1492
1493 if (!adev->gfx.config.backend_enable_mask ||
1494 adev->gfx.config.num_rbs >= num_rb_pipes)
1495 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1496 else
1497 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1498 adev->gfx.config.backend_enable_mask,
1499 num_rb_pipes);
1500
1501 /* cache the values for userspace */
1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1504 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1505 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1506 RREG32(mmCC_RB_BACKEND_DISABLE);
1507 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1508 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1509 adev->gfx.config.rb_config[i][j].raster_config =
1510 RREG32(mmPA_SC_RASTER_CONFIG);
1511 }
1512 }
1513 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1514 mutex_unlock(&adev->grbm_idx_mutex);
1515 }
1516
gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)1517 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1518 u32 bitmap)
1519 {
1520 u32 data;
1521
1522 if (!bitmap)
1523 return;
1524
1525 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1526 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1527
1528 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1529 }
1530
gfx_v6_0_get_cu_enabled(struct amdgpu_device * adev)1531 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1532 {
1533 u32 data, mask;
1534
1535 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1536 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1537
1538 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1539 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1540 }
1541
1542
gfx_v6_0_setup_spi(struct amdgpu_device * adev)1543 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1544 {
1545 int i, j, k;
1546 u32 data, mask;
1547 u32 active_cu = 0;
1548
1549 mutex_lock(&adev->grbm_idx_mutex);
1550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1552 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1553 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1554 active_cu = gfx_v6_0_get_cu_enabled(adev);
1555
1556 mask = 1;
1557 for (k = 0; k < 16; k++) {
1558 mask <<= k;
1559 if (active_cu & mask) {
1560 data &= ~mask;
1561 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1562 break;
1563 }
1564 }
1565 }
1566 }
1567 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1568 mutex_unlock(&adev->grbm_idx_mutex);
1569 }
1570
gfx_v6_0_config_init(struct amdgpu_device * adev)1571 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1572 {
1573 adev->gfx.config.double_offchip_lds_buf = 0;
1574 }
1575
gfx_v6_0_constants_init(struct amdgpu_device * adev)1576 static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1577 {
1578 u32 gb_addr_config = 0;
1579 u32 mc_arb_ramcfg;
1580 u32 sx_debug_1;
1581 u32 hdp_host_path_cntl;
1582 u32 tmp;
1583
1584 switch (adev->asic_type) {
1585 case CHIP_TAHITI:
1586 adev->gfx.config.max_shader_engines = 2;
1587 adev->gfx.config.max_tile_pipes = 12;
1588 adev->gfx.config.max_cu_per_sh = 8;
1589 adev->gfx.config.max_sh_per_se = 2;
1590 adev->gfx.config.max_backends_per_se = 4;
1591 adev->gfx.config.max_texture_channel_caches = 12;
1592 adev->gfx.config.max_gprs = 256;
1593 adev->gfx.config.max_gs_threads = 32;
1594 adev->gfx.config.max_hw_contexts = 8;
1595
1596 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1597 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1598 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1599 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1600 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1601 break;
1602 case CHIP_PITCAIRN:
1603 adev->gfx.config.max_shader_engines = 2;
1604 adev->gfx.config.max_tile_pipes = 8;
1605 adev->gfx.config.max_cu_per_sh = 5;
1606 adev->gfx.config.max_sh_per_se = 2;
1607 adev->gfx.config.max_backends_per_se = 4;
1608 adev->gfx.config.max_texture_channel_caches = 8;
1609 adev->gfx.config.max_gprs = 256;
1610 adev->gfx.config.max_gs_threads = 32;
1611 adev->gfx.config.max_hw_contexts = 8;
1612
1613 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1614 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1615 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1616 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1617 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1618 break;
1619 case CHIP_VERDE:
1620 adev->gfx.config.max_shader_engines = 1;
1621 adev->gfx.config.max_tile_pipes = 4;
1622 adev->gfx.config.max_cu_per_sh = 5;
1623 adev->gfx.config.max_sh_per_se = 2;
1624 adev->gfx.config.max_backends_per_se = 4;
1625 adev->gfx.config.max_texture_channel_caches = 4;
1626 adev->gfx.config.max_gprs = 256;
1627 adev->gfx.config.max_gs_threads = 32;
1628 adev->gfx.config.max_hw_contexts = 8;
1629
1630 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1631 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1632 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1633 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1634 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1635 break;
1636 case CHIP_OLAND:
1637 adev->gfx.config.max_shader_engines = 1;
1638 adev->gfx.config.max_tile_pipes = 4;
1639 adev->gfx.config.max_cu_per_sh = 6;
1640 adev->gfx.config.max_sh_per_se = 1;
1641 adev->gfx.config.max_backends_per_se = 2;
1642 adev->gfx.config.max_texture_channel_caches = 4;
1643 adev->gfx.config.max_gprs = 256;
1644 adev->gfx.config.max_gs_threads = 16;
1645 adev->gfx.config.max_hw_contexts = 8;
1646
1647 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1648 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1649 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1650 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1651 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1652 break;
1653 case CHIP_HAINAN:
1654 adev->gfx.config.max_shader_engines = 1;
1655 adev->gfx.config.max_tile_pipes = 4;
1656 adev->gfx.config.max_cu_per_sh = 5;
1657 adev->gfx.config.max_sh_per_se = 1;
1658 adev->gfx.config.max_backends_per_se = 1;
1659 adev->gfx.config.max_texture_channel_caches = 2;
1660 adev->gfx.config.max_gprs = 256;
1661 adev->gfx.config.max_gs_threads = 16;
1662 adev->gfx.config.max_hw_contexts = 8;
1663
1664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1665 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1666 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1667 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1668 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1669 break;
1670 default:
1671 BUG();
1672 break;
1673 }
1674
1675 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1676 WREG32(mmSRBM_INT_CNTL, 1);
1677 WREG32(mmSRBM_INT_ACK, 1);
1678
1679 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1680
1681 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1682 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1683
1684 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1685 adev->gfx.config.mem_max_burst_length_bytes = 256;
1686 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1687 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1688 if (adev->gfx.config.mem_row_size_in_kb > 4)
1689 adev->gfx.config.mem_row_size_in_kb = 4;
1690 adev->gfx.config.shader_engine_tile_size = 32;
1691 adev->gfx.config.num_gpus = 1;
1692 adev->gfx.config.multi_gpu_tile_size = 64;
1693
1694 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1695 switch (adev->gfx.config.mem_row_size_in_kb) {
1696 case 1:
1697 default:
1698 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1699 break;
1700 case 2:
1701 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1702 break;
1703 case 4:
1704 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1705 break;
1706 }
1707 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1708 if (adev->gfx.config.max_shader_engines == 2)
1709 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1710 adev->gfx.config.gb_addr_config = gb_addr_config;
1711
1712 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1713 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1714 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1715 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1716 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1717 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1718
1719 #if 0
1720 if (adev->has_uvd) {
1721 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1722 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1723 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1724 }
1725 #endif
1726 gfx_v6_0_tiling_mode_table_init(adev);
1727
1728 gfx_v6_0_setup_rb(adev);
1729
1730 gfx_v6_0_setup_spi(adev);
1731
1732 gfx_v6_0_get_cu_info(adev);
1733 gfx_v6_0_config_init(adev);
1734
1735 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1736 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1737 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1738 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1739
1740 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1741 WREG32(mmSX_DEBUG_1, sx_debug_1);
1742
1743 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1744
1745 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1746 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1747 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1748 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1749
1750 WREG32(mmVGT_NUM_INSTANCES, 1);
1751 WREG32(mmCP_PERFMON_CNTL, 0);
1752 WREG32(mmSQ_CONFIG, 0);
1753 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1754 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1755
1756 WREG32(mmVGT_CACHE_INVALIDATION,
1757 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1758 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1759
1760 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1761 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1762
1763 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1764 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1765 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1766 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1767 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1768 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1769 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1770 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1771
1772 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1773 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1774
1775 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1776 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1777
1778 udelay(50);
1779 }
1780
1781
gfx_v6_0_scratch_init(struct amdgpu_device * adev)1782 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1783 {
1784 adev->gfx.scratch.num_reg = 8;
1785 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1786 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1787 }
1788
gfx_v6_0_ring_test_ring(struct amdgpu_ring * ring)1789 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1790 {
1791 struct amdgpu_device *adev = ring->adev;
1792 uint32_t scratch;
1793 uint32_t tmp = 0;
1794 unsigned i;
1795 int r;
1796
1797 r = amdgpu_gfx_scratch_get(adev, &scratch);
1798 if (r)
1799 return r;
1800
1801 WREG32(scratch, 0xCAFEDEAD);
1802
1803 r = amdgpu_ring_alloc(ring, 3);
1804 if (r)
1805 goto error_free_scratch;
1806
1807 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1808 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1809 amdgpu_ring_write(ring, 0xDEADBEEF);
1810 amdgpu_ring_commit(ring);
1811
1812 for (i = 0; i < adev->usec_timeout; i++) {
1813 tmp = RREG32(scratch);
1814 if (tmp == 0xDEADBEEF)
1815 break;
1816 udelay(1);
1817 }
1818
1819 if (i >= adev->usec_timeout)
1820 r = -ETIMEDOUT;
1821
1822 error_free_scratch:
1823 amdgpu_gfx_scratch_free(adev, scratch);
1824 return r;
1825 }
1826
gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring * ring)1827 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1828 {
1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1830 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1831 EVENT_INDEX(0));
1832 }
1833
gfx_v6_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1834 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1835 u64 seq, unsigned flags)
1836 {
1837 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1838 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1839 /* flush read cache over gart */
1840 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1841 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1842 amdgpu_ring_write(ring, 0);
1843 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1844 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1845 PACKET3_TC_ACTION_ENA |
1846 PACKET3_SH_KCACHE_ACTION_ENA |
1847 PACKET3_SH_ICACHE_ACTION_ENA);
1848 amdgpu_ring_write(ring, 0xFFFFFFFF);
1849 amdgpu_ring_write(ring, 0);
1850 amdgpu_ring_write(ring, 10); /* poll interval */
1851 /* EVENT_WRITE_EOP - flush caches, send int */
1852 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1853 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1854 amdgpu_ring_write(ring, addr & 0xfffffffc);
1855 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1856 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1857 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1858 amdgpu_ring_write(ring, lower_32_bits(seq));
1859 amdgpu_ring_write(ring, upper_32_bits(seq));
1860 }
1861
gfx_v6_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1862 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1863 struct amdgpu_job *job,
1864 struct amdgpu_ib *ib,
1865 uint32_t flags)
1866 {
1867 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1868 u32 header, control = 0;
1869
1870 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1871 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1872 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1873 amdgpu_ring_write(ring, 0);
1874 }
1875
1876 if (ib->flags & AMDGPU_IB_FLAG_CE)
1877 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1878 else
1879 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1880
1881 control |= ib->length_dw | (vmid << 24);
1882
1883 amdgpu_ring_write(ring, header);
1884 amdgpu_ring_write(ring,
1885 #ifdef __BIG_ENDIAN
1886 (2 << 0) |
1887 #endif
1888 (ib->gpu_addr & 0xFFFFFFFC));
1889 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1890 amdgpu_ring_write(ring, control);
1891 }
1892
1893 /**
1894 * gfx_v6_0_ring_test_ib - basic ring IB test
1895 *
1896 * @ring: amdgpu_ring structure holding ring information
1897 *
1898 * Allocate an IB and execute it on the gfx ring (SI).
1899 * Provides a basic gfx ring test to verify that IBs are working.
1900 * Returns 0 on success, error on failure.
1901 */
gfx_v6_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)1902 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1903 {
1904 struct amdgpu_device *adev = ring->adev;
1905 struct amdgpu_ib ib;
1906 struct dma_fence *f = NULL;
1907 uint32_t scratch;
1908 uint32_t tmp = 0;
1909 long r;
1910
1911 r = amdgpu_gfx_scratch_get(adev, &scratch);
1912 if (r)
1913 return r;
1914
1915 WREG32(scratch, 0xCAFEDEAD);
1916 memset(&ib, 0, sizeof(ib));
1917 r = amdgpu_ib_get(adev, NULL, 256,
1918 AMDGPU_IB_POOL_DIRECT, &ib);
1919 if (r)
1920 goto err1;
1921
1922 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1923 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1924 ib.ptr[2] = 0xDEADBEEF;
1925 ib.length_dw = 3;
1926
1927 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1928 if (r)
1929 goto err2;
1930
1931 r = dma_fence_wait_timeout(f, false, timeout);
1932 if (r == 0) {
1933 r = -ETIMEDOUT;
1934 goto err2;
1935 } else if (r < 0) {
1936 goto err2;
1937 }
1938 tmp = RREG32(scratch);
1939 if (tmp == 0xDEADBEEF)
1940 r = 0;
1941 else
1942 r = -EINVAL;
1943
1944 err2:
1945 amdgpu_ib_free(adev, &ib, NULL);
1946 dma_fence_put(f);
1947 err1:
1948 amdgpu_gfx_scratch_free(adev, scratch);
1949 return r;
1950 }
1951
gfx_v6_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)1952 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1953 {
1954 if (enable) {
1955 WREG32(mmCP_ME_CNTL, 0);
1956 } else {
1957 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1958 CP_ME_CNTL__PFP_HALT_MASK |
1959 CP_ME_CNTL__CE_HALT_MASK));
1960 WREG32(mmSCRATCH_UMSK, 0);
1961 }
1962 udelay(50);
1963 }
1964
gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device * adev)1965 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1966 {
1967 unsigned i;
1968 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1969 const struct gfx_firmware_header_v1_0 *ce_hdr;
1970 const struct gfx_firmware_header_v1_0 *me_hdr;
1971 const __le32 *fw_data;
1972 u32 fw_size;
1973
1974 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1975 return -EINVAL;
1976
1977 gfx_v6_0_cp_gfx_enable(adev, false);
1978 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1979 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1980 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1981
1982 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1983 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1984 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1985
1986 /* PFP */
1987 fw_data = (const __le32 *)
1988 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1989 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1990 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1991 for (i = 0; i < fw_size; i++)
1992 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1993 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1994
1995 /* CE */
1996 fw_data = (const __le32 *)
1997 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1998 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1999 WREG32(mmCP_CE_UCODE_ADDR, 0);
2000 for (i = 0; i < fw_size; i++)
2001 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2002 WREG32(mmCP_CE_UCODE_ADDR, 0);
2003
2004 /* ME */
2005 fw_data = (const __be32 *)
2006 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2007 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2008 WREG32(mmCP_ME_RAM_WADDR, 0);
2009 for (i = 0; i < fw_size; i++)
2010 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2011 WREG32(mmCP_ME_RAM_WADDR, 0);
2012
2013 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2014 WREG32(mmCP_CE_UCODE_ADDR, 0);
2015 WREG32(mmCP_ME_RAM_WADDR, 0);
2016 WREG32(mmCP_ME_RAM_RADDR, 0);
2017 return 0;
2018 }
2019
gfx_v6_0_cp_gfx_start(struct amdgpu_device * adev)2020 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2021 {
2022 const struct cs_section_def *sect = NULL;
2023 const struct cs_extent_def *ext = NULL;
2024 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2025 int r, i;
2026
2027 r = amdgpu_ring_alloc(ring, 7 + 4);
2028 if (r) {
2029 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2030 return r;
2031 }
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2033 amdgpu_ring_write(ring, 0x1);
2034 amdgpu_ring_write(ring, 0x0);
2035 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2036 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2037 amdgpu_ring_write(ring, 0);
2038 amdgpu_ring_write(ring, 0);
2039
2040 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2041 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2042 amdgpu_ring_write(ring, 0xc000);
2043 amdgpu_ring_write(ring, 0xe000);
2044 amdgpu_ring_commit(ring);
2045
2046 gfx_v6_0_cp_gfx_enable(adev, true);
2047
2048 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2049 if (r) {
2050 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2051 return r;
2052 }
2053
2054 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2055 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2056
2057 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2058 for (ext = sect->section; ext->extent != NULL; ++ext) {
2059 if (sect->id == SECT_CONTEXT) {
2060 amdgpu_ring_write(ring,
2061 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2062 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2063 for (i = 0; i < ext->reg_count; i++)
2064 amdgpu_ring_write(ring, ext->extent[i]);
2065 }
2066 }
2067 }
2068
2069 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2070 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2071
2072 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2073 amdgpu_ring_write(ring, 0);
2074
2075 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2076 amdgpu_ring_write(ring, 0x00000316);
2077 amdgpu_ring_write(ring, 0x0000000e);
2078 amdgpu_ring_write(ring, 0x00000010);
2079
2080 amdgpu_ring_commit(ring);
2081
2082 return 0;
2083 }
2084
gfx_v6_0_cp_gfx_resume(struct amdgpu_device * adev)2085 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2086 {
2087 struct amdgpu_ring *ring;
2088 u32 tmp;
2089 u32 rb_bufsz;
2090 int r;
2091 u64 rptr_addr;
2092
2093 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2094 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2095
2096 /* Set the write pointer delay */
2097 WREG32(mmCP_RB_WPTR_DELAY, 0);
2098
2099 WREG32(mmCP_DEBUG, 0);
2100 WREG32(mmSCRATCH_ADDR, 0);
2101
2102 /* ring 0 - compute and gfx */
2103 /* Set ring buffer size */
2104 ring = &adev->gfx.gfx_ring[0];
2105 rb_bufsz = order_base_2(ring->ring_size / 8);
2106 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2107
2108 #ifdef __BIG_ENDIAN
2109 tmp |= BUF_SWAP_32BIT;
2110 #endif
2111 WREG32(mmCP_RB0_CNTL, tmp);
2112
2113 /* Initialize the ring buffer's read and write pointers */
2114 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2115 ring->wptr = 0;
2116 WREG32(mmCP_RB0_WPTR, ring->wptr);
2117
2118 /* set the wb address whether it's enabled or not */
2119 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2120 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2121 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2122
2123 WREG32(mmSCRATCH_UMSK, 0);
2124
2125 mdelay(1);
2126 WREG32(mmCP_RB0_CNTL, tmp);
2127
2128 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2129
2130 /* start the rings */
2131 gfx_v6_0_cp_gfx_start(adev);
2132 r = amdgpu_ring_test_helper(ring);
2133 if (r)
2134 return r;
2135
2136 return 0;
2137 }
2138
gfx_v6_0_ring_get_rptr(struct amdgpu_ring * ring)2139 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2140 {
2141 return ring->adev->wb.wb[ring->rptr_offs];
2142 }
2143
gfx_v6_0_ring_get_wptr(struct amdgpu_ring * ring)2144 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2145 {
2146 struct amdgpu_device *adev = ring->adev;
2147
2148 if (ring == &adev->gfx.gfx_ring[0])
2149 return RREG32(mmCP_RB0_WPTR);
2150 else if (ring == &adev->gfx.compute_ring[0])
2151 return RREG32(mmCP_RB1_WPTR);
2152 else if (ring == &adev->gfx.compute_ring[1])
2153 return RREG32(mmCP_RB2_WPTR);
2154 else
2155 BUG();
2156 }
2157
gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)2158 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2159 {
2160 struct amdgpu_device *adev = ring->adev;
2161
2162 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2163 (void)RREG32(mmCP_RB0_WPTR);
2164 }
2165
gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring * ring)2166 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2167 {
2168 struct amdgpu_device *adev = ring->adev;
2169
2170 if (ring == &adev->gfx.compute_ring[0]) {
2171 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2172 (void)RREG32(mmCP_RB1_WPTR);
2173 } else if (ring == &adev->gfx.compute_ring[1]) {
2174 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2175 (void)RREG32(mmCP_RB2_WPTR);
2176 } else {
2177 BUG();
2178 }
2179
2180 }
2181
gfx_v6_0_cp_compute_resume(struct amdgpu_device * adev)2182 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2183 {
2184 struct amdgpu_ring *ring;
2185 u32 tmp;
2186 u32 rb_bufsz;
2187 int i, r;
2188 u64 rptr_addr;
2189
2190 /* ring1 - compute only */
2191 /* Set ring buffer size */
2192
2193 ring = &adev->gfx.compute_ring[0];
2194 rb_bufsz = order_base_2(ring->ring_size / 8);
2195 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2196 #ifdef __BIG_ENDIAN
2197 tmp |= BUF_SWAP_32BIT;
2198 #endif
2199 WREG32(mmCP_RB1_CNTL, tmp);
2200
2201 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2202 ring->wptr = 0;
2203 WREG32(mmCP_RB1_WPTR, ring->wptr);
2204
2205 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2206 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2207 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2208
2209 mdelay(1);
2210 WREG32(mmCP_RB1_CNTL, tmp);
2211 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2212
2213 ring = &adev->gfx.compute_ring[1];
2214 rb_bufsz = order_base_2(ring->ring_size / 8);
2215 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2216 #ifdef __BIG_ENDIAN
2217 tmp |= BUF_SWAP_32BIT;
2218 #endif
2219 WREG32(mmCP_RB2_CNTL, tmp);
2220
2221 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2222 ring->wptr = 0;
2223 WREG32(mmCP_RB2_WPTR, ring->wptr);
2224 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2225 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2226 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2227
2228 mdelay(1);
2229 WREG32(mmCP_RB2_CNTL, tmp);
2230 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2231
2232
2233 for (i = 0; i < 2; i++) {
2234 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2235 if (r)
2236 return r;
2237 }
2238
2239 return 0;
2240 }
2241
gfx_v6_0_cp_enable(struct amdgpu_device * adev,bool enable)2242 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2243 {
2244 gfx_v6_0_cp_gfx_enable(adev, enable);
2245 }
2246
gfx_v6_0_cp_load_microcode(struct amdgpu_device * adev)2247 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2248 {
2249 return gfx_v6_0_cp_gfx_load_microcode(adev);
2250 }
2251
gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)2252 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2253 bool enable)
2254 {
2255 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2256 u32 mask;
2257 int i;
2258
2259 if (enable)
2260 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2261 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2262 else
2263 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2264 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2265 WREG32(mmCP_INT_CNTL_RING0, tmp);
2266
2267 if (!enable) {
2268 /* read a gfx register */
2269 tmp = RREG32(mmDB_DEPTH_INFO);
2270
2271 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2272 for (i = 0; i < adev->usec_timeout; i++) {
2273 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2274 break;
2275 udelay(1);
2276 }
2277 }
2278 }
2279
gfx_v6_0_cp_resume(struct amdgpu_device * adev)2280 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2281 {
2282 int r;
2283
2284 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2285
2286 r = gfx_v6_0_cp_load_microcode(adev);
2287 if (r)
2288 return r;
2289
2290 r = gfx_v6_0_cp_gfx_resume(adev);
2291 if (r)
2292 return r;
2293 r = gfx_v6_0_cp_compute_resume(adev);
2294 if (r)
2295 return r;
2296
2297 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2298
2299 return 0;
2300 }
2301
gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)2302 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2303 {
2304 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2305 uint32_t seq = ring->fence_drv.sync_seq;
2306 uint64_t addr = ring->fence_drv.gpu_addr;
2307
2308 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2309 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2310 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2311 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2312 amdgpu_ring_write(ring, addr & 0xfffffffc);
2313 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2314 amdgpu_ring_write(ring, seq);
2315 amdgpu_ring_write(ring, 0xffffffff);
2316 amdgpu_ring_write(ring, 4); /* poll interval */
2317
2318 if (usepfp) {
2319 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2320 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2321 amdgpu_ring_write(ring, 0);
2322 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2323 amdgpu_ring_write(ring, 0);
2324 }
2325 }
2326
gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)2327 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2328 unsigned vmid, uint64_t pd_addr)
2329 {
2330 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2331
2332 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2333
2334 /* wait for the invalidate to complete */
2335 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2336 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2337 WAIT_REG_MEM_ENGINE(0))); /* me */
2338 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2339 amdgpu_ring_write(ring, 0);
2340 amdgpu_ring_write(ring, 0); /* ref */
2341 amdgpu_ring_write(ring, 0); /* mask */
2342 amdgpu_ring_write(ring, 0x20); /* poll interval */
2343
2344 if (usepfp) {
2345 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2346 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2347 amdgpu_ring_write(ring, 0x0);
2348
2349 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2350 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2351 amdgpu_ring_write(ring, 0);
2352 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2353 amdgpu_ring_write(ring, 0);
2354 }
2355 }
2356
gfx_v6_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)2357 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2358 uint32_t reg, uint32_t val)
2359 {
2360 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2361
2362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2364 WRITE_DATA_DST_SEL(0)));
2365 amdgpu_ring_write(ring, reg);
2366 amdgpu_ring_write(ring, 0);
2367 amdgpu_ring_write(ring, val);
2368 }
2369
gfx_v6_0_rlc_init(struct amdgpu_device * adev)2370 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2371 {
2372 const u32 *src_ptr;
2373 volatile u32 *dst_ptr;
2374 u32 dws;
2375 u64 reg_list_mc_addr;
2376 const struct cs_section_def *cs_data;
2377 int r;
2378
2379 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2380 adev->gfx.rlc.reg_list_size =
2381 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2382
2383 adev->gfx.rlc.cs_data = si_cs_data;
2384 src_ptr = adev->gfx.rlc.reg_list;
2385 dws = adev->gfx.rlc.reg_list_size;
2386 cs_data = adev->gfx.rlc.cs_data;
2387
2388 if (src_ptr) {
2389 /* init save restore block */
2390 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2391 if (r)
2392 return r;
2393 }
2394
2395 if (cs_data) {
2396 /* clear state block */
2397 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2398 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2399
2400 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2401 AMDGPU_GEM_DOMAIN_VRAM,
2402 &adev->gfx.rlc.clear_state_obj,
2403 &adev->gfx.rlc.clear_state_gpu_addr,
2404 (void **)&adev->gfx.rlc.cs_ptr);
2405 if (r) {
2406 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2407 amdgpu_gfx_rlc_fini(adev);
2408 return r;
2409 }
2410
2411 /* set up the cs buffer */
2412 dst_ptr = adev->gfx.rlc.cs_ptr;
2413 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2414 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2415 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2416 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2417 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2418 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2419 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2420 }
2421
2422 return 0;
2423 }
2424
gfx_v6_0_enable_lbpw(struct amdgpu_device * adev,bool enable)2425 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2426 {
2427 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2428
2429 if (!enable) {
2430 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2431 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2432 }
2433 }
2434
gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device * adev)2435 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2436 {
2437 int i;
2438
2439 for (i = 0; i < adev->usec_timeout; i++) {
2440 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2441 break;
2442 udelay(1);
2443 }
2444
2445 for (i = 0; i < adev->usec_timeout; i++) {
2446 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2447 break;
2448 udelay(1);
2449 }
2450 }
2451
gfx_v6_0_update_rlc(struct amdgpu_device * adev,u32 rlc)2452 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2453 {
2454 u32 tmp;
2455
2456 tmp = RREG32(mmRLC_CNTL);
2457 if (tmp != rlc)
2458 WREG32(mmRLC_CNTL, rlc);
2459 }
2460
gfx_v6_0_halt_rlc(struct amdgpu_device * adev)2461 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2462 {
2463 u32 data, orig;
2464
2465 orig = data = RREG32(mmRLC_CNTL);
2466
2467 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2468 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2469 WREG32(mmRLC_CNTL, data);
2470
2471 gfx_v6_0_wait_for_rlc_serdes(adev);
2472 }
2473
2474 return orig;
2475 }
2476
gfx_v6_0_rlc_stop(struct amdgpu_device * adev)2477 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2478 {
2479 WREG32(mmRLC_CNTL, 0);
2480
2481 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2482 gfx_v6_0_wait_for_rlc_serdes(adev);
2483 }
2484
gfx_v6_0_rlc_start(struct amdgpu_device * adev)2485 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2486 {
2487 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2488
2489 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2490
2491 udelay(50);
2492 }
2493
gfx_v6_0_rlc_reset(struct amdgpu_device * adev)2494 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2495 {
2496 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2497 udelay(50);
2498 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2499 udelay(50);
2500 }
2501
gfx_v6_0_lbpw_supported(struct amdgpu_device * adev)2502 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2503 {
2504 u32 tmp;
2505
2506 /* Enable LBPW only for DDR3 */
2507 tmp = RREG32(mmMC_SEQ_MISC0);
2508 if ((tmp & 0xF0000000) == 0xB0000000)
2509 return true;
2510 return false;
2511 }
2512
gfx_v6_0_init_cg(struct amdgpu_device * adev)2513 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2514 {
2515 }
2516
gfx_v6_0_rlc_resume(struct amdgpu_device * adev)2517 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2518 {
2519 u32 i;
2520 const struct rlc_firmware_header_v1_0 *hdr;
2521 const __le32 *fw_data;
2522 u32 fw_size;
2523
2524
2525 if (!adev->gfx.rlc_fw)
2526 return -EINVAL;
2527
2528 adev->gfx.rlc.funcs->stop(adev);
2529 adev->gfx.rlc.funcs->reset(adev);
2530 gfx_v6_0_init_pg(adev);
2531 gfx_v6_0_init_cg(adev);
2532
2533 WREG32(mmRLC_RL_BASE, 0);
2534 WREG32(mmRLC_RL_SIZE, 0);
2535 WREG32(mmRLC_LB_CNTL, 0);
2536 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2537 WREG32(mmRLC_LB_CNTR_INIT, 0);
2538 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2539
2540 WREG32(mmRLC_MC_CNTL, 0);
2541 WREG32(mmRLC_UCODE_CNTL, 0);
2542
2543 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2544 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2545 fw_data = (const __le32 *)
2546 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2547
2548 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2549
2550 for (i = 0; i < fw_size; i++) {
2551 WREG32(mmRLC_UCODE_ADDR, i);
2552 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2553 }
2554 WREG32(mmRLC_UCODE_ADDR, 0);
2555
2556 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2557 adev->gfx.rlc.funcs->start(adev);
2558
2559 return 0;
2560 }
2561
gfx_v6_0_enable_cgcg(struct amdgpu_device * adev,bool enable)2562 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2563 {
2564 u32 data, orig, tmp;
2565
2566 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2567
2568 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2569 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2570
2571 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2572
2573 tmp = gfx_v6_0_halt_rlc(adev);
2574
2575 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2576 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2577 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2578
2579 gfx_v6_0_wait_for_rlc_serdes(adev);
2580 gfx_v6_0_update_rlc(adev, tmp);
2581
2582 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2583
2584 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2585 } else {
2586 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2587
2588 RREG32(mmCB_CGTT_SCLK_CTRL);
2589 RREG32(mmCB_CGTT_SCLK_CTRL);
2590 RREG32(mmCB_CGTT_SCLK_CTRL);
2591 RREG32(mmCB_CGTT_SCLK_CTRL);
2592
2593 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2594 }
2595
2596 if (orig != data)
2597 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2598
2599 }
2600
gfx_v6_0_enable_mgcg(struct amdgpu_device * adev,bool enable)2601 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2602 {
2603
2604 u32 data, orig, tmp = 0;
2605
2606 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2607 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2608 data = 0x96940200;
2609 if (orig != data)
2610 WREG32(mmCGTS_SM_CTRL_REG, data);
2611
2612 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2613 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2614 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2615 if (orig != data)
2616 WREG32(mmCP_MEM_SLP_CNTL, data);
2617 }
2618
2619 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2620 data &= 0xffffffc0;
2621 if (orig != data)
2622 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2623
2624 tmp = gfx_v6_0_halt_rlc(adev);
2625
2626 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2627 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2628 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2629
2630 gfx_v6_0_update_rlc(adev, tmp);
2631 } else {
2632 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2633 data |= 0x00000003;
2634 if (orig != data)
2635 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2636
2637 data = RREG32(mmCP_MEM_SLP_CNTL);
2638 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2639 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2640 WREG32(mmCP_MEM_SLP_CNTL, data);
2641 }
2642 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2643 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2644 if (orig != data)
2645 WREG32(mmCGTS_SM_CTRL_REG, data);
2646
2647 tmp = gfx_v6_0_halt_rlc(adev);
2648
2649 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2651 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2652
2653 gfx_v6_0_update_rlc(adev, tmp);
2654 }
2655 }
2656 /*
2657 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2658 bool enable)
2659 {
2660 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2661 if (enable) {
2662 gfx_v6_0_enable_mgcg(adev, true);
2663 gfx_v6_0_enable_cgcg(adev, true);
2664 } else {
2665 gfx_v6_0_enable_cgcg(adev, false);
2666 gfx_v6_0_enable_mgcg(adev, false);
2667 }
2668 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2669 }
2670 */
2671
gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device * adev,bool enable)2672 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2673 bool enable)
2674 {
2675 }
2676
gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device * adev,bool enable)2677 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2678 bool enable)
2679 {
2680 }
2681
gfx_v6_0_enable_cp_pg(struct amdgpu_device * adev,bool enable)2682 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2683 {
2684 u32 data, orig;
2685
2686 orig = data = RREG32(mmRLC_PG_CNTL);
2687 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2688 data &= ~0x8000;
2689 else
2690 data |= 0x8000;
2691 if (orig != data)
2692 WREG32(mmRLC_PG_CNTL, data);
2693 }
2694
gfx_v6_0_enable_gds_pg(struct amdgpu_device * adev,bool enable)2695 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2696 {
2697 }
2698 /*
2699 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2700 {
2701 const __le32 *fw_data;
2702 volatile u32 *dst_ptr;
2703 int me, i, max_me = 4;
2704 u32 bo_offset = 0;
2705 u32 table_offset, table_size;
2706
2707 if (adev->asic_type == CHIP_KAVERI)
2708 max_me = 5;
2709
2710 if (adev->gfx.rlc.cp_table_ptr == NULL)
2711 return;
2712
2713 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2714 for (me = 0; me < max_me; me++) {
2715 if (me == 0) {
2716 const struct gfx_firmware_header_v1_0 *hdr =
2717 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2718 fw_data = (const __le32 *)
2719 (adev->gfx.ce_fw->data +
2720 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2721 table_offset = le32_to_cpu(hdr->jt_offset);
2722 table_size = le32_to_cpu(hdr->jt_size);
2723 } else if (me == 1) {
2724 const struct gfx_firmware_header_v1_0 *hdr =
2725 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2726 fw_data = (const __le32 *)
2727 (adev->gfx.pfp_fw->data +
2728 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2729 table_offset = le32_to_cpu(hdr->jt_offset);
2730 table_size = le32_to_cpu(hdr->jt_size);
2731 } else if (me == 2) {
2732 const struct gfx_firmware_header_v1_0 *hdr =
2733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2734 fw_data = (const __le32 *)
2735 (adev->gfx.me_fw->data +
2736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2737 table_offset = le32_to_cpu(hdr->jt_offset);
2738 table_size = le32_to_cpu(hdr->jt_size);
2739 } else if (me == 3) {
2740 const struct gfx_firmware_header_v1_0 *hdr =
2741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2742 fw_data = (const __le32 *)
2743 (adev->gfx.mec_fw->data +
2744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2745 table_offset = le32_to_cpu(hdr->jt_offset);
2746 table_size = le32_to_cpu(hdr->jt_size);
2747 } else {
2748 const struct gfx_firmware_header_v1_0 *hdr =
2749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2750 fw_data = (const __le32 *)
2751 (adev->gfx.mec2_fw->data +
2752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2753 table_offset = le32_to_cpu(hdr->jt_offset);
2754 table_size = le32_to_cpu(hdr->jt_size);
2755 }
2756
2757 for (i = 0; i < table_size; i ++) {
2758 dst_ptr[bo_offset + i] =
2759 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2760 }
2761
2762 bo_offset += table_size;
2763 }
2764 }
2765 */
gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device * adev,bool enable)2766 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2767 bool enable)
2768 {
2769 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2770 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2771 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2772 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2773 } else {
2774 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2775 (void)RREG32(mmDB_RENDER_CONTROL);
2776 }
2777 }
2778
gfx_v6_0_init_ao_cu_mask(struct amdgpu_device * adev)2779 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2780 {
2781 u32 tmp;
2782
2783 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2784
2785 tmp = RREG32(mmRLC_MAX_PG_CU);
2786 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2787 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2788 WREG32(mmRLC_MAX_PG_CU, tmp);
2789 }
2790
gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device * adev,bool enable)2791 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2792 bool enable)
2793 {
2794 u32 data, orig;
2795
2796 orig = data = RREG32(mmRLC_PG_CNTL);
2797 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2798 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2799 else
2800 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2801 if (orig != data)
2802 WREG32(mmRLC_PG_CNTL, data);
2803 }
2804
gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device * adev,bool enable)2805 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2806 bool enable)
2807 {
2808 u32 data, orig;
2809
2810 orig = data = RREG32(mmRLC_PG_CNTL);
2811 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2812 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2813 else
2814 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2815 if (orig != data)
2816 WREG32(mmRLC_PG_CNTL, data);
2817 }
2818
gfx_v6_0_init_gfx_cgpg(struct amdgpu_device * adev)2819 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2820 {
2821 u32 tmp;
2822
2823 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2824 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2825 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2826
2827 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2828 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2829 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2830 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2831 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2832 }
2833
gfx_v6_0_update_gfx_pg(struct amdgpu_device * adev,bool enable)2834 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2835 {
2836 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2837 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2838 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2839 }
2840
gfx_v6_0_get_csb_size(struct amdgpu_device * adev)2841 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2842 {
2843 u32 count = 0;
2844 const struct cs_section_def *sect = NULL;
2845 const struct cs_extent_def *ext = NULL;
2846
2847 if (adev->gfx.rlc.cs_data == NULL)
2848 return 0;
2849
2850 /* begin clear state */
2851 count += 2;
2852 /* context control state */
2853 count += 3;
2854
2855 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2856 for (ext = sect->section; ext->extent != NULL; ++ext) {
2857 if (sect->id == SECT_CONTEXT)
2858 count += 2 + ext->reg_count;
2859 else
2860 return 0;
2861 }
2862 }
2863 /* pa_sc_raster_config */
2864 count += 3;
2865 /* end clear state */
2866 count += 2;
2867 /* clear state */
2868 count += 2;
2869
2870 return count;
2871 }
2872
gfx_v6_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)2873 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2874 volatile u32 *buffer)
2875 {
2876 u32 count = 0, i;
2877 const struct cs_section_def *sect = NULL;
2878 const struct cs_extent_def *ext = NULL;
2879
2880 if (adev->gfx.rlc.cs_data == NULL)
2881 return;
2882 if (buffer == NULL)
2883 return;
2884
2885 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2886 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2887 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2888 buffer[count++] = cpu_to_le32(0x80000000);
2889 buffer[count++] = cpu_to_le32(0x80000000);
2890
2891 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2892 for (ext = sect->section; ext->extent != NULL; ++ext) {
2893 if (sect->id == SECT_CONTEXT) {
2894 buffer[count++] =
2895 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2896 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2897 for (i = 0; i < ext->reg_count; i++)
2898 buffer[count++] = cpu_to_le32(ext->extent[i]);
2899 } else {
2900 return;
2901 }
2902 }
2903 }
2904
2905 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2906 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2907 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2908
2909 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2910 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2911
2912 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2913 buffer[count++] = cpu_to_le32(0);
2914 }
2915
gfx_v6_0_init_pg(struct amdgpu_device * adev)2916 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2917 {
2918 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2919 AMD_PG_SUPPORT_GFX_SMG |
2920 AMD_PG_SUPPORT_GFX_DMG |
2921 AMD_PG_SUPPORT_CP |
2922 AMD_PG_SUPPORT_GDS |
2923 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2924 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2925 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2926 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2927 gfx_v6_0_init_gfx_cgpg(adev);
2928 gfx_v6_0_enable_cp_pg(adev, true);
2929 gfx_v6_0_enable_gds_pg(adev, true);
2930 } else {
2931 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2932 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2933
2934 }
2935 gfx_v6_0_init_ao_cu_mask(adev);
2936 gfx_v6_0_update_gfx_pg(adev, true);
2937 } else {
2938
2939 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2940 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2941 }
2942 }
2943
gfx_v6_0_fini_pg(struct amdgpu_device * adev)2944 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2945 {
2946 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2947 AMD_PG_SUPPORT_GFX_SMG |
2948 AMD_PG_SUPPORT_GFX_DMG |
2949 AMD_PG_SUPPORT_CP |
2950 AMD_PG_SUPPORT_GDS |
2951 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2952 gfx_v6_0_update_gfx_pg(adev, false);
2953 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2954 gfx_v6_0_enable_cp_pg(adev, false);
2955 gfx_v6_0_enable_gds_pg(adev, false);
2956 }
2957 }
2958 }
2959
gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device * adev)2960 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2961 {
2962 uint64_t clock;
2963
2964 mutex_lock(&adev->gfx.gpu_clock_mutex);
2965 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2966 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2967 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2968 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2969 return clock;
2970 }
2971
gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)2972 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2973 {
2974 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2975 gfx_v6_0_ring_emit_vgt_flush(ring);
2976 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2977 amdgpu_ring_write(ring, 0x80000000);
2978 amdgpu_ring_write(ring, 0);
2979 }
2980
2981
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)2982 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2983 {
2984 WREG32(mmSQ_IND_INDEX,
2985 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2986 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2987 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2988 (SQ_IND_INDEX__FORCE_READ_MASK));
2989 return RREG32(mmSQ_IND_DATA);
2990 }
2991
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)2992 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2993 uint32_t wave, uint32_t thread,
2994 uint32_t regno, uint32_t num, uint32_t *out)
2995 {
2996 WREG32(mmSQ_IND_INDEX,
2997 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2998 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2999 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3000 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3001 (SQ_IND_INDEX__FORCE_READ_MASK) |
3002 (SQ_IND_INDEX__AUTO_INCR_MASK));
3003 while (num--)
3004 *(out++) = RREG32(mmSQ_IND_DATA);
3005 }
3006
gfx_v6_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)3007 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3008 {
3009 /* type 0 wave data */
3010 dst[(*no_fields)++] = 0;
3011 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3029 }
3030
gfx_v6_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)3031 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3032 uint32_t wave, uint32_t start,
3033 uint32_t size, uint32_t *dst)
3034 {
3035 wave_read_regs(
3036 adev, simd, wave, 0,
3037 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3038 }
3039
gfx_v6_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm)3040 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3041 u32 me, u32 pipe, u32 q, u32 vm)
3042 {
3043 DRM_INFO("Not implemented\n");
3044 }
3045
3046 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3047 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3048 .select_se_sh = &gfx_v6_0_select_se_sh,
3049 .read_wave_data = &gfx_v6_0_read_wave_data,
3050 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3051 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3052 };
3053
3054 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3055 .init = gfx_v6_0_rlc_init,
3056 .resume = gfx_v6_0_rlc_resume,
3057 .stop = gfx_v6_0_rlc_stop,
3058 .reset = gfx_v6_0_rlc_reset,
3059 .start = gfx_v6_0_rlc_start
3060 };
3061
gfx_v6_0_early_init(void * handle)3062 static int gfx_v6_0_early_init(void *handle)
3063 {
3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065
3066 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3067 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3068 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3069 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3070 gfx_v6_0_set_ring_funcs(adev);
3071 gfx_v6_0_set_irq_funcs(adev);
3072
3073 return 0;
3074 }
3075
gfx_v6_0_sw_init(void * handle)3076 static int gfx_v6_0_sw_init(void *handle)
3077 {
3078 struct amdgpu_ring *ring;
3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3080 int i, r;
3081
3082 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3083 if (r)
3084 return r;
3085
3086 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3087 if (r)
3088 return r;
3089
3090 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3091 if (r)
3092 return r;
3093
3094 gfx_v6_0_scratch_init(adev);
3095
3096 r = gfx_v6_0_init_microcode(adev);
3097 if (r) {
3098 DRM_ERROR("Failed to load gfx firmware!\n");
3099 return r;
3100 }
3101
3102 r = adev->gfx.rlc.funcs->init(adev);
3103 if (r) {
3104 DRM_ERROR("Failed to init rlc BOs!\n");
3105 return r;
3106 }
3107
3108 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3109 ring = &adev->gfx.gfx_ring[i];
3110 ring->ring_obj = NULL;
3111 sprintf(ring->name, "gfx");
3112 r = amdgpu_ring_init(adev, ring, 1024,
3113 &adev->gfx.eop_irq,
3114 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
3115 AMDGPU_RING_PRIO_DEFAULT);
3116 if (r)
3117 return r;
3118 }
3119
3120 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3121 unsigned irq_type;
3122
3123 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3124 DRM_ERROR("Too many (%d) compute rings!\n", i);
3125 break;
3126 }
3127 ring = &adev->gfx.compute_ring[i];
3128 ring->ring_obj = NULL;
3129 ring->use_doorbell = false;
3130 ring->doorbell_index = 0;
3131 ring->me = 1;
3132 ring->pipe = i;
3133 ring->queue = i;
3134 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3135 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3136 r = amdgpu_ring_init(adev, ring, 1024,
3137 &adev->gfx.eop_irq, irq_type,
3138 AMDGPU_RING_PRIO_DEFAULT);
3139 if (r)
3140 return r;
3141 }
3142
3143 return r;
3144 }
3145
gfx_v6_0_sw_fini(void * handle)3146 static int gfx_v6_0_sw_fini(void *handle)
3147 {
3148 int i;
3149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3150
3151 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3152 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3153 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3154 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3155
3156 amdgpu_gfx_rlc_fini(adev);
3157
3158 return 0;
3159 }
3160
gfx_v6_0_hw_init(void * handle)3161 static int gfx_v6_0_hw_init(void *handle)
3162 {
3163 int r;
3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3165
3166 gfx_v6_0_constants_init(adev);
3167
3168 r = adev->gfx.rlc.funcs->resume(adev);
3169 if (r)
3170 return r;
3171
3172 r = gfx_v6_0_cp_resume(adev);
3173 if (r)
3174 return r;
3175
3176 adev->gfx.ce_ram_size = 0x8000;
3177
3178 return r;
3179 }
3180
gfx_v6_0_hw_fini(void * handle)3181 static int gfx_v6_0_hw_fini(void *handle)
3182 {
3183 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3184
3185 gfx_v6_0_cp_enable(adev, false);
3186 adev->gfx.rlc.funcs->stop(adev);
3187 gfx_v6_0_fini_pg(adev);
3188
3189 return 0;
3190 }
3191
gfx_v6_0_suspend(void * handle)3192 static int gfx_v6_0_suspend(void *handle)
3193 {
3194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3195
3196 return gfx_v6_0_hw_fini(adev);
3197 }
3198
gfx_v6_0_resume(void * handle)3199 static int gfx_v6_0_resume(void *handle)
3200 {
3201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3202
3203 return gfx_v6_0_hw_init(adev);
3204 }
3205
gfx_v6_0_is_idle(void * handle)3206 static bool gfx_v6_0_is_idle(void *handle)
3207 {
3208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3209
3210 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3211 return false;
3212 else
3213 return true;
3214 }
3215
gfx_v6_0_wait_for_idle(void * handle)3216 static int gfx_v6_0_wait_for_idle(void *handle)
3217 {
3218 unsigned i;
3219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3220
3221 for (i = 0; i < adev->usec_timeout; i++) {
3222 if (gfx_v6_0_is_idle(handle))
3223 return 0;
3224 udelay(1);
3225 }
3226 return -ETIMEDOUT;
3227 }
3228
gfx_v6_0_soft_reset(void * handle)3229 static int gfx_v6_0_soft_reset(void *handle)
3230 {
3231 return 0;
3232 }
3233
gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)3234 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3235 enum amdgpu_interrupt_state state)
3236 {
3237 u32 cp_int_cntl;
3238
3239 switch (state) {
3240 case AMDGPU_IRQ_STATE_DISABLE:
3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3242 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3243 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3244 break;
3245 case AMDGPU_IRQ_STATE_ENABLE:
3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3247 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3248 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3249 break;
3250 default:
3251 break;
3252 }
3253 }
3254
gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int ring,enum amdgpu_interrupt_state state)3255 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3256 int ring,
3257 enum amdgpu_interrupt_state state)
3258 {
3259 u32 cp_int_cntl;
3260 switch (state){
3261 case AMDGPU_IRQ_STATE_DISABLE:
3262 if (ring == 0) {
3263 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3264 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3265 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3266 break;
3267 } else {
3268 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3269 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3270 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3271 break;
3272
3273 }
3274 case AMDGPU_IRQ_STATE_ENABLE:
3275 if (ring == 0) {
3276 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3277 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3278 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3279 break;
3280 } else {
3281 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3282 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3283 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3284 break;
3285
3286 }
3287
3288 default:
3289 BUG();
3290 break;
3291
3292 }
3293 }
3294
gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3295 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3296 struct amdgpu_irq_src *src,
3297 unsigned type,
3298 enum amdgpu_interrupt_state state)
3299 {
3300 u32 cp_int_cntl;
3301
3302 switch (state) {
3303 case AMDGPU_IRQ_STATE_DISABLE:
3304 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3305 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3306 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3307 break;
3308 case AMDGPU_IRQ_STATE_ENABLE:
3309 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3310 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3311 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3312 break;
3313 default:
3314 break;
3315 }
3316
3317 return 0;
3318 }
3319
gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3320 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3321 struct amdgpu_irq_src *src,
3322 unsigned type,
3323 enum amdgpu_interrupt_state state)
3324 {
3325 u32 cp_int_cntl;
3326
3327 switch (state) {
3328 case AMDGPU_IRQ_STATE_DISABLE:
3329 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3330 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3331 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3332 break;
3333 case AMDGPU_IRQ_STATE_ENABLE:
3334 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3335 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3336 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3337 break;
3338 default:
3339 break;
3340 }
3341
3342 return 0;
3343 }
3344
gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)3345 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3346 struct amdgpu_irq_src *src,
3347 unsigned type,
3348 enum amdgpu_interrupt_state state)
3349 {
3350 switch (type) {
3351 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3352 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3353 break;
3354 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3355 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3356 break;
3357 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3358 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3359 break;
3360 default:
3361 break;
3362 }
3363 return 0;
3364 }
3365
gfx_v6_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3366 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3367 struct amdgpu_irq_src *source,
3368 struct amdgpu_iv_entry *entry)
3369 {
3370 switch (entry->ring_id) {
3371 case 0:
3372 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3373 break;
3374 case 1:
3375 case 2:
3376 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3377 break;
3378 default:
3379 break;
3380 }
3381 return 0;
3382 }
3383
gfx_v6_0_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)3384 static void gfx_v6_0_fault(struct amdgpu_device *adev,
3385 struct amdgpu_iv_entry *entry)
3386 {
3387 struct amdgpu_ring *ring;
3388
3389 switch (entry->ring_id) {
3390 case 0:
3391 ring = &adev->gfx.gfx_ring[0];
3392 break;
3393 case 1:
3394 case 2:
3395 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3396 break;
3397 default:
3398 return;
3399 }
3400 drm_sched_fault(&ring->sched);
3401 }
3402
gfx_v6_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3403 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3404 struct amdgpu_irq_src *source,
3405 struct amdgpu_iv_entry *entry)
3406 {
3407 DRM_ERROR("Illegal register access in command stream\n");
3408 gfx_v6_0_fault(adev, entry);
3409 return 0;
3410 }
3411
gfx_v6_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)3412 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3413 struct amdgpu_irq_src *source,
3414 struct amdgpu_iv_entry *entry)
3415 {
3416 DRM_ERROR("Illegal instruction in command stream\n");
3417 gfx_v6_0_fault(adev, entry);
3418 return 0;
3419 }
3420
gfx_v6_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)3421 static int gfx_v6_0_set_clockgating_state(void *handle,
3422 enum amd_clockgating_state state)
3423 {
3424 bool gate = false;
3425 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3426
3427 if (state == AMD_CG_STATE_GATE)
3428 gate = true;
3429
3430 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3431 if (gate) {
3432 gfx_v6_0_enable_mgcg(adev, true);
3433 gfx_v6_0_enable_cgcg(adev, true);
3434 } else {
3435 gfx_v6_0_enable_cgcg(adev, false);
3436 gfx_v6_0_enable_mgcg(adev, false);
3437 }
3438 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3439
3440 return 0;
3441 }
3442
gfx_v6_0_set_powergating_state(void * handle,enum amd_powergating_state state)3443 static int gfx_v6_0_set_powergating_state(void *handle,
3444 enum amd_powergating_state state)
3445 {
3446 bool gate = false;
3447 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3448
3449 if (state == AMD_PG_STATE_GATE)
3450 gate = true;
3451
3452 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3453 AMD_PG_SUPPORT_GFX_SMG |
3454 AMD_PG_SUPPORT_GFX_DMG |
3455 AMD_PG_SUPPORT_CP |
3456 AMD_PG_SUPPORT_GDS |
3457 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3458 gfx_v6_0_update_gfx_pg(adev, gate);
3459 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3460 gfx_v6_0_enable_cp_pg(adev, gate);
3461 gfx_v6_0_enable_gds_pg(adev, gate);
3462 }
3463 }
3464
3465 return 0;
3466 }
3467
gfx_v6_0_emit_mem_sync(struct amdgpu_ring * ring)3468 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3469 {
3470 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3471 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3472 PACKET3_TC_ACTION_ENA |
3473 PACKET3_SH_KCACHE_ACTION_ENA |
3474 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
3475 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
3476 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3477 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3478 }
3479
3480 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3481 .name = "gfx_v6_0",
3482 .early_init = gfx_v6_0_early_init,
3483 .late_init = NULL,
3484 .sw_init = gfx_v6_0_sw_init,
3485 .sw_fini = gfx_v6_0_sw_fini,
3486 .hw_init = gfx_v6_0_hw_init,
3487 .hw_fini = gfx_v6_0_hw_fini,
3488 .suspend = gfx_v6_0_suspend,
3489 .resume = gfx_v6_0_resume,
3490 .is_idle = gfx_v6_0_is_idle,
3491 .wait_for_idle = gfx_v6_0_wait_for_idle,
3492 .soft_reset = gfx_v6_0_soft_reset,
3493 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3494 .set_powergating_state = gfx_v6_0_set_powergating_state,
3495 };
3496
3497 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3498 .type = AMDGPU_RING_TYPE_GFX,
3499 .align_mask = 0xff,
3500 .nop = 0x80000000,
3501 .support_64bit_ptrs = false,
3502 .get_rptr = gfx_v6_0_ring_get_rptr,
3503 .get_wptr = gfx_v6_0_ring_get_wptr,
3504 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3505 .emit_frame_size =
3506 5 + 5 + /* hdp flush / invalidate */
3507 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3508 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3509 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3510 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3511 5, /* SURFACE_SYNC */
3512 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3513 .emit_ib = gfx_v6_0_ring_emit_ib,
3514 .emit_fence = gfx_v6_0_ring_emit_fence,
3515 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3516 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3517 .test_ring = gfx_v6_0_ring_test_ring,
3518 .test_ib = gfx_v6_0_ring_test_ib,
3519 .insert_nop = amdgpu_ring_insert_nop,
3520 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3521 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3522 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3523 };
3524
3525 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3526 .type = AMDGPU_RING_TYPE_COMPUTE,
3527 .align_mask = 0xff,
3528 .nop = 0x80000000,
3529 .get_rptr = gfx_v6_0_ring_get_rptr,
3530 .get_wptr = gfx_v6_0_ring_get_wptr,
3531 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3532 .emit_frame_size =
3533 5 + 5 + /* hdp flush / invalidate */
3534 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3535 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3536 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3537 5, /* SURFACE_SYNC */
3538 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3539 .emit_ib = gfx_v6_0_ring_emit_ib,
3540 .emit_fence = gfx_v6_0_ring_emit_fence,
3541 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3542 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3543 .test_ring = gfx_v6_0_ring_test_ring,
3544 .test_ib = gfx_v6_0_ring_test_ib,
3545 .insert_nop = amdgpu_ring_insert_nop,
3546 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3547 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3548 };
3549
gfx_v6_0_set_ring_funcs(struct amdgpu_device * adev)3550 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3551 {
3552 int i;
3553
3554 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3555 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3556 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3557 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3558 }
3559
3560 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3561 .set = gfx_v6_0_set_eop_interrupt_state,
3562 .process = gfx_v6_0_eop_irq,
3563 };
3564
3565 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3566 .set = gfx_v6_0_set_priv_reg_fault_state,
3567 .process = gfx_v6_0_priv_reg_irq,
3568 };
3569
3570 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3571 .set = gfx_v6_0_set_priv_inst_fault_state,
3572 .process = gfx_v6_0_priv_inst_irq,
3573 };
3574
gfx_v6_0_set_irq_funcs(struct amdgpu_device * adev)3575 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3576 {
3577 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3578 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3579
3580 adev->gfx.priv_reg_irq.num_types = 1;
3581 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3582
3583 adev->gfx.priv_inst_irq.num_types = 1;
3584 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3585 }
3586
gfx_v6_0_get_cu_info(struct amdgpu_device * adev)3587 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3588 {
3589 int i, j, k, counter, active_cu_number = 0;
3590 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3591 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3592 unsigned disable_masks[4 * 2];
3593 u32 ao_cu_num;
3594
3595 if (adev->flags & AMD_IS_APU)
3596 ao_cu_num = 2;
3597 else
3598 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3599
3600 memset(cu_info, 0, sizeof(*cu_info));
3601
3602 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3603
3604 mutex_lock(&adev->grbm_idx_mutex);
3605 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3606 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3607 mask = 1;
3608 ao_bitmap = 0;
3609 counter = 0;
3610 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3611 if (i < 4 && j < 2)
3612 gfx_v6_0_set_user_cu_inactive_bitmap(
3613 adev, disable_masks[i * 2 + j]);
3614 bitmap = gfx_v6_0_get_cu_enabled(adev);
3615 cu_info->bitmap[i][j] = bitmap;
3616
3617 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3618 if (bitmap & mask) {
3619 if (counter < ao_cu_num)
3620 ao_bitmap |= mask;
3621 counter ++;
3622 }
3623 mask <<= 1;
3624 }
3625 active_cu_number += counter;
3626 if (i < 2 && j < 2)
3627 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3628 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3629 }
3630 }
3631
3632 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3633 mutex_unlock(&adev->grbm_idx_mutex);
3634
3635 cu_info->number = active_cu_number;
3636 cu_info->ao_cu_mask = ao_cu_mask;
3637 }
3638
3639 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3640 {
3641 .type = AMD_IP_BLOCK_TYPE_GFX,
3642 .major = 6,
3643 .minor = 0,
3644 .rev = 0,
3645 .funcs = &gfx_v6_0_ip_funcs,
3646 };
3647
