Lines Matching full:gfx
47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
932 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
995 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
996 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
997 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1130 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1131 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1132 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1133 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1134 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1135 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
1136 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1137 adev->gfx.rlc_fw = NULL; in gfx_v9_0_free_microcode()
1138 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
1139 adev->gfx.mec_fw = NULL; in gfx_v9_0_free_microcode()
1140 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
1141 adev->gfx.mec2_fw = NULL; in gfx_v9_0_free_microcode()
1143 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1150 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_ext_microcode()
1151 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
1152 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
1153 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v9_0_init_rlc_ext_microcode()
1154 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v9_0_init_rlc_ext_microcode()
1155 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
1156 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
1157 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
1158 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v9_0_init_rlc_ext_microcode()
1159 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
1160 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
1161 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
1162 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in gfx_v9_0_init_rlc_ext_microcode()
1163 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v9_0_init_rlc_ext_microcode()
1169 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1170 adev->gfx.mec_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
1173 ((adev->gfx.mec_fw_version < 0x000001a5) || in gfx_v9_0_check_fw_write_wait()
1174 (adev->gfx.mec_feature_version < 46) || in gfx_v9_0_check_fw_write_wait()
1175 (adev->gfx.pfp_fw_version < 0x000000b7) || in gfx_v9_0_check_fw_write_wait()
1176 (adev->gfx.pfp_feature_version < 46))) in gfx_v9_0_check_fw_write_wait()
1181 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1182 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1183 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1184 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1185 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1187 if ((adev->gfx.mec_fw_version >= 0x00000193) && in gfx_v9_0_check_fw_write_wait()
1188 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1189 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1192 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1193 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1194 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1195 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1196 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1198 if ((adev->gfx.mec_fw_version >= 0x00000196) && in gfx_v9_0_check_fw_write_wait()
1199 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1200 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1203 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1204 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1205 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1206 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1207 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1209 if ((adev->gfx.mec_fw_version >= 0x00000197) && in gfx_v9_0_check_fw_write_wait()
1210 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1211 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1214 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1215 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1216 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1217 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1218 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1220 if ((adev->gfx.mec_fw_version >= 0x00000192) && in gfx_v9_0_check_fw_write_wait()
1221 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1222 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1225 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1226 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1288 adev->gfx.rlc_fw_version < 531) || in gfx_v9_0_check_if_need_gfxoff()
1289 (adev->gfx.rlc_feature_version < 1) || in gfx_v9_0_check_if_need_gfxoff()
1290 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1319 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1322 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1325 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1326 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1327 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1330 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1333 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1336 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1337 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1338 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1341 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1344 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1348 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1349 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1354 info->fw = adev->gfx.pfp_fw; in gfx_v9_0_init_cp_gfx_microcode()
1361 info->fw = adev->gfx.me_fw; in gfx_v9_0_init_cp_gfx_microcode()
1368 info->fw = adev->gfx.ce_fw; in gfx_v9_0_init_cp_gfx_microcode()
1379 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1380 adev->gfx.pfp_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1381 release_firmware(adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1382 adev->gfx.me_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1383 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1384 adev->gfx.ce_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1423 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v9_0_init_rlc_microcode()
1426 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1427 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()
1432 adev->gfx.rlc.is_rlc_v2_1 = true; in gfx_v9_0_init_rlc_microcode()
1434 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v9_0_init_rlc_microcode()
1435 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v9_0_init_rlc_microcode()
1436 adev->gfx.rlc.save_and_restore_offset = in gfx_v9_0_init_rlc_microcode()
1438 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v9_0_init_rlc_microcode()
1440 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v9_0_init_rlc_microcode()
1442 adev->gfx.rlc.reg_restore_list_size = in gfx_v9_0_init_rlc_microcode()
1444 adev->gfx.rlc.reg_list_format_start = in gfx_v9_0_init_rlc_microcode()
1446 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v9_0_init_rlc_microcode()
1448 adev->gfx.rlc.starting_offsets_start = in gfx_v9_0_init_rlc_microcode()
1450 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v9_0_init_rlc_microcode()
1452 adev->gfx.rlc.reg_list_size_bytes = in gfx_v9_0_init_rlc_microcode()
1454 adev->gfx.rlc.register_list_format = in gfx_v9_0_init_rlc_microcode()
1455 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v9_0_init_rlc_microcode()
1456 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v9_0_init_rlc_microcode()
1457 if (!adev->gfx.rlc.register_list_format) { in gfx_v9_0_init_rlc_microcode()
1464 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v9_0_init_rlc_microcode()
1465 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_rlc_microcode()
1467 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v9_0_init_rlc_microcode()
1471 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v9_0_init_rlc_microcode()
1472 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_rlc_microcode()
1474 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v9_0_init_rlc_microcode()
1480 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1485 if (adev->gfx.rlc.is_rlc_v2_1 && in gfx_v9_0_init_rlc_microcode()
1486 adev->gfx.rlc.save_restore_list_cntl_size_bytes && in gfx_v9_0_init_rlc_microcode()
1487 adev->gfx.rlc.save_restore_list_gpm_size_bytes && in gfx_v9_0_init_rlc_microcode()
1488 adev->gfx.rlc.save_restore_list_srm_size_bytes) { in gfx_v9_0_init_rlc_microcode()
1491 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1493 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1497 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1499 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1503 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1505 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1514 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1515 adev->gfx.rlc_fw = NULL; in gfx_v9_0_init_rlc_microcode()
1530 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_compute_microcode()
1533 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1536 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_init_cp_compute_microcode()
1537 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_compute_microcode()
1538 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_compute_microcode()
1542 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_compute_microcode()
1544 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1548 adev->gfx.mec2_fw->data; in gfx_v9_0_init_cp_compute_microcode()
1549 adev->gfx.mec2_fw_version = in gfx_v9_0_init_cp_compute_microcode()
1551 adev->gfx.mec2_feature_version = in gfx_v9_0_init_cp_compute_microcode()
1555 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1561 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_cp_compute_microcode()
1569 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_cp_compute_microcode()
1573 if (adev->gfx.mec2_fw) { in gfx_v9_0_init_cp_compute_microcode()
1576 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_cp_compute_microcode()
1583 for all GFX V9 asic and above */ in gfx_v9_0_init_cp_compute_microcode()
1588 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_cp_compute_microcode()
1603 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1604 adev->gfx.mec_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1605 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1606 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1702 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1714 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1738 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_0_init_always_on_cu_mask()
1752 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_init_always_on_cu_mask()
1753 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
1759 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_init_always_on_cu_mask()
1893 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1895 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1906 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
1924 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v9_0_rlc_init()
1925 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v9_0_rlc_init()
1932 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1933 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1947 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v9_0_mec_init()
1951 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()
1955 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1956 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1966 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1967 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1970 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()
1973 (adev->gfx.mec_fw->data + in gfx_v9_0_mec_init()
1979 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1980 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1990 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1991 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
2096 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; in gfx_v9_0_gpu_early_init()
2100 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2101 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2102 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2103 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2104 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2108 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2111 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2114 DRM_INFO("fix gfx.config for vega12\n"); in gfx_v9_0_gpu_early_init()
2117 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2118 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2119 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2120 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2121 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2131 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2132 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2133 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2134 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2135 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2142 adev->gfx.funcs = &gfx_v9_4_gfx_funcs; in gfx_v9_0_gpu_early_init()
2143 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2144 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2145 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2146 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
2147 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2153 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
2154 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
2155 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
2156 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v9_0_gpu_early_init()
2157 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
2167 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
2169 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()
2171 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2175 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
2176 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()
2178 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()
2180 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2183 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()
2185 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2188 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()
2190 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2193 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
2195 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2198 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
2200 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
2211 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2214 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2224 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
2229 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
2235 &adev->gfx.eop_irq, irq_type, hw_prio); in gfx_v9_0_compute_ring_init()
2252 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2255 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2259 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
2260 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2263 …_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); in gfx_v9_0_sw_init()
2269 &adev->gfx.priv_reg_irq); in gfx_v9_0_sw_init()
2275 &adev->gfx.priv_inst_irq); in gfx_v9_0_sw_init()
2281 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2287 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2291 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v9_0_sw_init()
2297 DRM_ERROR("Failed to load gfx firmware!\n"); in gfx_v9_0_sw_init()
2301 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_0_sw_init()
2313 /* set up the gfx ring */ in gfx_v9_0_sw_init()
2314 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v9_0_sw_init()
2315 ring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_sw_init()
2318 sprintf(ring->name, "gfx"); in gfx_v9_0_sw_init()
2324 &adev->gfx.eop_irq, in gfx_v9_0_sw_init()
2333 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
2334 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
2335 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
2356 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
2366 adev->gfx.ce_ram_size = 0x8000; in gfx_v9_0_sw_init()
2383 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_sw_fini()
2384 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v9_0_sw_fini()
2385 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()
2386 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v9_0_sw_fini()
2389 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v9_0_sw_fini()
2393 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); in gfx_v9_0_sw_fini()
2395 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_sw_fini()
2396 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_sw_fini()
2397 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_sw_fini()
2443 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
2444 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2454 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
2455 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2458 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_setup_rb()
2459 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2462 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2469 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v9_0_setup_rb()
2470 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
2517 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA in gfx_v9_0_init_gds_vmid()
2556 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_constants_init()
2557 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_constants_init()
2600 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_wait_for_rlc_serdes()
2601 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
2647 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v9_0_init_csb()
2650 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2652 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
2654 adev->gfx.rlc.clear_state_size); in gfx_v9_0_init_csb()
2707 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v9_1_init_rlc_save_restore_list()
2708 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v9_1_init_rlc_save_restore_list()
2715 adev->gfx.rlc.reg_list_format_direct_reg_list_length, in gfx_v9_1_init_rlc_save_restore_list()
2716 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v9_1_init_rlc_save_restore_list()
2731 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v9_1_init_rlc_save_restore_list()
2733 adev->gfx.rlc.register_restore[i]); in gfx_v9_1_init_rlc_save_restore_list()
2737 adev->gfx.rlc.reg_list_format_start); in gfx_v9_1_init_rlc_save_restore_list()
2740 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) in gfx_v9_1_init_rlc_save_restore_list()
2745 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { in gfx_v9_1_init_rlc_save_restore_list()
2767 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v9_1_init_rlc_save_restore_list()
2770 adev->gfx.rlc.reg_restore_list_size); in gfx_v9_1_init_rlc_save_restore_list()
2775 adev->gfx.rlc.starting_offsets_start); in gfx_v9_1_init_rlc_save_restore_list()
2938 /* read any GFX register to wake up GFX */ in gfx_v9_0_enable_gfx_pipeline_powergating()
2976 if (adev->gfx.rlc.is_rlc_v2_1) { in gfx_v9_0_init_pg()
2990 adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v9_0_init_pg()
3030 rlc_ucode_ver, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_start()
3048 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
3051 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_rlc_load_microcode()
3054 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v9_0_rlc_load_microcode()
3062 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
3076 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_rlc_resume()
3107 adev->gfx.rlc.funcs->start(adev); in gfx_v9_0_rlc_resume()
3131 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
3135 adev->gfx.pfp_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3137 adev->gfx.ce_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3139 adev->gfx.me_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3149 (adev->gfx.pfp_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3155 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3159 (adev->gfx.ce_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3165 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3169 (adev->gfx.me_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3175 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3182 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_start()
3188 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
3256 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_resume()
3319 adev->gfx.kiq.ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3331 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
3336 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()
3340 (adev->gfx.mec_fw->data + in gfx_v9_0_cp_compute_load_microcode()
3348 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
3350 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
3360 adev->gfx.mec_fw_version); in gfx_v9_0_cp_compute_load_microcode()
3697 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
3698 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3720 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
3721 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3731 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v9_0_kcq_init_queue()
3743 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3744 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3747 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3748 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3766 ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_resume()
3791 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()
3792 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kcq_resume()
3849 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_resume()
3855 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()
3856 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_cp_resume()
3901 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v9_0_hw_init()
3916 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v9_0_hw_fini()
3917 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_hw_fini()
3918 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_hw_fini()
3941 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, in gfx_v9_0_hw_fini()
3942 adev->gfx.kiq.ring.pipe, in gfx_v9_0_hw_fini()
3943 adev->gfx.kiq.ring.queue, 0); in gfx_v9_0_hw_fini()
3944 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); in gfx_v9_0_hw_fini()
3950 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_hw_fini()
4023 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_soft_reset()
4026 /* Disable GFX parsing/prefetching */ in gfx_v9_0_soft_reset()
4058 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v9_0_kiq_read_clock()
4131 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4139 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4411 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gds_workarounds()
4458 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gpr_workarounds()
4465 int compute_dim_x = adev->gfx.config.max_shader_engines * in gfx_v9_0_do_edc_gpr_workarounds()
4466 adev->gfx.config.max_cu_per_sh * in gfx_v9_0_do_edc_gpr_workarounds()
4467 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
4469 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; in gfx_v9_0_do_edc_gpr_workarounds()
4633 adev->gfx.num_gfx_rings = 0; in gfx_v9_0_early_init()
4635 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; in gfx_v9_0_early_init()
4636 adev->gfx.num_compute_rings = amdgpu_num_kcq; in gfx_v9_0_early_init()
4668 if (adev->gfx.funcs && in gfx_v9_0_ecc_late_init()
4669 adev->gfx.funcs->reset_ras_error_count) in gfx_v9_0_ecc_late_init()
4670 adev->gfx.funcs->reset_ras_error_count(adev); in gfx_v9_0_ecc_late_init()
4684 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_late_init()
4688 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_late_init()
4798 /* MGLS is a global flag to control all MGLS in GFX */ in gfx_v9_0_update_medium_grain_clock_gating()
4959 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
4968 /* === CGCG /CGLS for GFX 3D Only === */ in gfx_v9_0_update_gfx_clock_gating()
5066 /* update gfx cgpg state */ in gfx_v9_0_set_powergating_state()
5469 /* set load_per_context_state & load_gfx_sh_regs for GFX */ in gfx_v9_ring_emit_cntxcntl()
5566 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; in gfx_v9_0_ring_emit_reg_write_reg_wait()
5786 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v9_0_eop_irq()
5790 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()
5791 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_eop_irq()
5816 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v9_0_fault()
5820 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()
5821 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_fault()
6308 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
6316 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", in gfx_v9_0_ras_error_inject()
6522 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
6534 dev_info(adev->dev, "GFX SubBlock %s, " in gfx_v9_0_ras_error_count()
6802 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; in gfx_v9_0_set_ring_funcs()
6804 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_set_ring_funcs()
6805 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
6807 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
6808 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; in gfx_v9_0_set_ring_funcs()
6834 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
6835 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; in gfx_v9_0_set_irq_funcs()
6837 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
6838 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; in gfx_v9_0_set_irq_funcs()
6840 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
6841 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; in gfx_v9_0_set_irq_funcs()
6843 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ in gfx_v9_0_set_irq_funcs()
6844 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; in gfx_v9_0_set_irq_funcs()
6856 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; in gfx_v9_0_set_rlc_funcs()
6932 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
6950 if (adev->gfx.config.max_shader_engines * in gfx_v9_0_get_cu_info()
6951 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
6955 adev->gfx.config.max_shader_engines, in gfx_v9_0_get_cu_info()
6956 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
6959 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_get_cu_info()
6960 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
6966 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); in gfx_v9_0_get_cu_info()
6983 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()
6985 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()