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/Linux-v6.1/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
36 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
84 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
107 /* Relative to priv->regmap */
110 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
128 * A lane is described by the following bitfields:
129 * [ 1- 0]: COMPHY polarity invertion
[all …]
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
39 * When accessing common PHY lane registers directly, we need to shift by 1,
40 * since the registers are 16-bit.
68 #define SPEED_PLL_MASK GENMASK(7, 2)
137 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
155 #define MODE_MARGIN_OVERRIDE BIT(2)
160 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
174 * This register is not from PHY lane register space. It only exists in the
175 * indirect register space, before the actual PHY lane 2 registers. So the
[all …]
Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
28 #define COMPHY_STAT1_PLL_RDY_RX BIT(2)
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
63 if (priv->conf) { in a38x_set_conf()
64 conf = readl_relaxed(priv->conf); in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
69 writel(conf, priv->conf); in a38x_set_conf()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
44 /* 10GBASE-R and 10GBASE-X4/X2 */
48 #define MV88E6393X_10G_INT_LINK_CHANGE BIT(2)
51 /* 1000BASE-X and SGMII */
75 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
113 int lane, unsigned int mode,
117 int lane, unsigned int mode,
121 int lane, struct phylink_link_state *state);
123 int lane, struct phylink_link_state *state);
125 int lane, struct phylink_link_state *state);
[all …]
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
56 state->link = false; in mv88e6xxx_serdes_pcs_get_state()
64 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_serdes_pcs_get_state()
65 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_serdes_pcs_get_state()
72 state->duplex = status & in mv88e6xxx_serdes_pcs_get_state()
77 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_serdes_pcs_get_state()
[all …]
/Linux-v6.1/sound/soc/tegra/
Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
47 ASRC_STREAM_REG_DEFAULTS(2),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
107 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
[all …]
/Linux-v6.1/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
[all …]
/Linux-v6.1/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
11 #define LYNX_28G_NUM_PLL 2
23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
44 /* Per SerDes lane registers */
45 /* Lane a General Control Register */
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
50 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
54 /* Lane a Tx Reset Control Register */
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
[all …]
/Linux-v6.1/drivers/phy/tegra/
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
[all …]
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
80 #define USB2_OTG_PD_DR BIT(2)
135 #define UTMI_LS SPEED(2)
147 #define FAKE_USBOP_EN BIT(2)
[all …]
Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
66 USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \
68 SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
106 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
146 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
188 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
276 (((_port) <= 2) ? (_offset1) : (_offset2))
[all …]
/Linux-v6.1/drivers/thunderbolt/
Dlc.c1 // SPDX-License-Identifier: GPL-2.0
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
18 if (!sw->cap_lc) in tb_lc_read_uuid()
19 return -EINVAL; in tb_lc_read_uuid()
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 if (!sw->cap_lc) in read_lc_desc()
26 return -EINVAL; in read_lc_desc()
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
32 struct tb_switch *sw = port->sw; in find_port_lc_cap()
43 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap()
[all …]
/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
24 * 2. DP only mode:
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
58 #define CMN_SSM_BANDGAP (0x21 << 2)
59 #define CMN_SSM_BIAS (0x22 << 2)
[all …]
/Linux-v6.1/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
137 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
[all …]
/Linux-v6.1/drivers/media/platform/ti/omap3isp/
Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
/Linux-v6.1/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
[all …]
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
31 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
36 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
43 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
50 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_read_lttpr_phy_caps()
53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
54 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
56 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
61 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, in intel_dp_read_lttpr_phy_caps()
63 encoder->base.base.id, encoder->base.name, in intel_dp_read_lttpr_phy_caps()
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c50 link->ctx->logger
133 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_cr_training_aux_rd_interval()
160 link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
171 case 2: return 8000; in get_eq_training_aux_rd_interval()
276 struct dpcd_caps *rx_caps = &link->dpcd_caps; in decide_eq_training_pattern()
281 enc_caps = &link_enc->features; in decide_eq_training_pattern()
285 if (enc_caps->flags.bits.IS_TPS4_CAPABLE && in decide_eq_training_pattern()
286 rx_caps->max_down_spread.bits.TPS4_SUPPORTED) in decide_eq_training_pattern()
288 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE && in decide_eq_training_pattern()
289 rx_caps->max_ln_count.bits.TPS3_SUPPORTED) in decide_eq_training_pattern()
[all …]
/Linux-v6.1/drivers/pinctrl/tegra/
Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
88 struct phy *phys[2];
96 writel(value, padctl->regs + offset); in padctl_writel()
102 return readl(padctl->regs + offset); in padctl_readl()
109 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
117 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
126 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
127 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
[all …]
/Linux-v6.1/drivers/phy/mediatek/
Dphy-mtk-pcie.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-consumer.h>
15 #include "phy-mtk-io.h"
25 #define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
50 * struct mtk_pcie_phy_data - phy data for each SoC
51 * @num_lanes: supported lane numbers
60 * struct mtk_pcie_phy - PCIe phy driver main structure
67 * @efuse: pointer to eFuse data for each lane
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
Dphy-mvebu-comphy.txt2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
17 * 4 entries for Armada 3700 along with the corresponding reg-names
20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
23 - marvell,system-controller: should contain a phandle to the system
[all …]

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