Lines Matching +full:2 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
48 /* Max 2 lanes per a PHY unit */
49 #define MAX_LANE 2
168 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
189 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
206 (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
267 /* PHY lane CSR accessing from SDS indirectly */
348 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
447 (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
456 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
465 (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
488 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
506 CLK_INT_SING = 2, /* Internal single ended */
512 MODE_PCIE = 2,
519 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
525 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
526 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
527 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
547 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
596 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
607 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
613 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
659 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
668 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
674 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
727 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
737 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
752 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
855 /* Configure lane for 20-bits */ in xgene_phy_sata_cfg_cmu_core()
943 int lane; in xgene_phy_sata_cfg_lanes() local
945 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
946 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
949 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
953 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
956 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
959 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
960 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
961 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
966 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
970 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
972 /* Configure Tx for 20-bits */ in xgene_phy_sata_cfg_lanes()
973 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
975 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
978 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
984 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ in xgene_phy_sata_cfg_lanes()
985 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
987 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
988 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
990 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
991 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
993 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
994 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
995 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
998 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
1000 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1008 /* Configure Rx for 20-bits */ in xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1012 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1015 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1021 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1024 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1026 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1029 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1033 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1036 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1039 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1041 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1044 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1046 /* Set Eye Monitor counter width to 12-bit */ in xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1051 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1053 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1059 reg = RXTX_REG81 + i * 2; in xgene_phy_sata_cfg_lanes()
1060 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1064 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1069 reg = RXTX_REG96 + i * 2; in xgene_phy_sata_cfg_lanes()
1070 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1074 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1079 reg = RXTX_REG99 + i * 2; in xgene_phy_sata_cfg_lanes()
1080 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1084 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1087 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1089 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1091 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1093 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1095 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1096 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1098 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1099 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1101 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1103 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1105 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1107 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1109 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1111 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1121 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1128 reg = RXTX_REG148 + i * 2; in xgene_phy_sata_cfg_lanes()
1129 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1138 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1187 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN in xgene_phy_cal_rdy_chk()
1217 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1220 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1223 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1225 return -1; in xgene_phy_cal_rdy_chk()
1227 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1230 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1240 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1255 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1260 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1264 /* Release PHY lane from reset (active high) */ in xgene_phy_hw_init_sata()
1274 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1277 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1295 /* Set Rx/Tx 20-bit */ in xgene_phy_hw_init_sata()
1308 } while (--i > 0); in xgene_phy_hw_init_sata()
1311 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1322 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1324 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1329 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1330 ctx->mode); in xgene_phy_hw_initialize()
1331 return -ENODEV; in xgene_phy_hw_initialize()
1340 * Calibrate the receiver signal path offset in two steps - summar and
1343 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal() argument
1371 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1378 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1387 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1394 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1397 /* Configure the PHY lane for calibration */ in xgene_phy_force_lat_summer_cal()
1398 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1399 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1400 serdes_clrbits(ctx, lane, RXTX_REG4, in xgene_phy_force_lat_summer_cal()
1402 serdes_clrbits(ctx, lane, RXTX_REG7, in xgene_phy_force_lat_summer_cal()
1405 serdes_wr(ctx, lane, serdes_reg[i].reg, in xgene_phy_force_lat_summer_cal()
1409 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd() argument
1412 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1415 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1420 return (accum + (samples / 2)) / samples; in xgene_phy_get_avg()
1423 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val() argument
1437 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1438 lane); in xgene_phy_gen_avg_val()
1440 /* Enable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1441 serdes_setbits(ctx, lane, RXTX_REG12, in xgene_phy_gen_avg_val()
1444 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1446 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1450 * Calibrate the receiver signal path offset in two steps - summar in xgene_phy_gen_avg_val()
1457 xgene_phy_force_lat_summer_cal(ctx, lane); in xgene_phy_gen_avg_val()
1459 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1464 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1469 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1473 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1477 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1493 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1494 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1497 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1500 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1503 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1507 xgene_phy_reset_rxd(ctx, lane); in xgene_phy_gen_avg_val()
1511 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1516 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1518 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1523 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1525 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1530 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1532 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1537 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1540 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1543 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1545 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1546 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1551 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1556 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1559 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1561 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1562 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1564 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1566 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1567 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1569 /* Disable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()
1574 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1576 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()
1587 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1592 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1594 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1595 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1596 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1603 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1617 if (args->args_count <= 0) in xgene_phy_xlate()
1618 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1619 if (args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1620 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1622 ctx->mode = args->args[0]; in xgene_phy_xlate()
1623 return ctx->phy; in xgene_phy_xlate()
1633 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, in xgene_phy_get_param()
1658 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1660 return -ENOMEM; in xgene_phy_probe()
1662 ctx->dev = &pdev->dev; in xgene_phy_probe()
1664 ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); in xgene_phy_probe()
1665 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1666 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1669 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1672 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", in xgene_phy_probe()
1673 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1674 xgene_phy_get_param(pdev, "apm,tx-eye-direction", in xgene_phy_probe()
1675 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1676 xgene_phy_get_param(pdev, "apm,tx-boost-gain", in xgene_phy_probe()
1677 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1678 xgene_phy_get_param(pdev, "apm,tx-amplitude", in xgene_phy_probe()
1679 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1680 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", in xgene_phy_probe()
1681 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1682 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", in xgene_phy_probe()
1683 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1684 xgene_phy_get_param(pdev, "apm,tx-post-cursor", in xgene_phy_probe()
1685 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1686 xgene_phy_get_param(pdev, "apm,tx-speed", in xgene_phy_probe()
1687 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1689 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1693 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1694 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1695 dev_dbg(&pdev->dev, "Failed to create PHY\n"); in xgene_phy_probe()
1696 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1698 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1700 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()
1705 {.compatible = "apm,xgene-phy",},
1713 .name = "xgene-phy",
1719 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");