Lines Matching +full:2 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
11 #define LYNX_28G_NUM_PLL 2
23 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
44 /* Per SerDes lane registers */
45 /* Lane a General Control Register */
46 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
50 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
54 /* Lane a Tx Reset Control Register */
55 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
60 /* Lane a Tx General Control Register */
61 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
70 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
72 /* Lane a Rx Reset Control Register */
73 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40) argument
79 /* Lane a Rx General Control Register */
80 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44) argument
90 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) argument
92 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50) argument
93 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) argument
94 #define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58) argument
96 #define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) argument
98 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) argument
103 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) argument
130 struct lynx_28g_lane lane[LYNX_28G_NUM_LANE]; member
138 void __iomem *reg = priv->base + off; in lynx_28g_rmw()
147 #define lynx_28g_lane_rmw(lane, reg, val, mask) \ argument
148 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
150 #define lynx_28g_lane_read(lane, reg) \ argument
151 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
153 ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
160 if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl)) in lynx_28g_supports_interface()
163 if (test_bit(intf, priv->pll[i].supported)) in lynx_28g_supports_interface()
177 pll = &priv->pll[i]; in lynx_28g_pll_get()
179 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_get()
182 if (test_bit(intf, pll->supported)) in lynx_28g_pll_get()
189 static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane, in lynx_28g_lane_set_nrate() argument
193 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_lane_set_nrate()
199 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK); in lynx_28g_lane_set_nrate()
200 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK); in lynx_28g_lane_set_nrate()
210 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK); in lynx_28g_lane_set_nrate()
211 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK); in lynx_28g_lane_set_nrate()
222 static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane, in lynx_28g_lane_set_pll() argument
225 if (pll->id == 0) { in lynx_28g_lane_set_pll()
226 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK); in lynx_28g_lane_set_pll()
227 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK); in lynx_28g_lane_set_pll()
229 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK); in lynx_28g_lane_set_pll()
230 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK); in lynx_28g_lane_set_pll()
234 static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane) in lynx_28g_cleanup_lane() argument
236 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_cleanup_lane()
237 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_cleanup_lane()
240 switch (lane->interface) { in lynx_28g_cleanup_lane()
257 static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane) in lynx_28g_lane_set_sgmii() argument
259 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_sgmii()
260 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_lane_set_sgmii()
263 lynx_28g_cleanup_lane(lane); in lynx_28g_lane_set_sgmii()
265 /* Setup the lane to run in SGMII */ in lynx_28g_lane_set_sgmii()
271 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK); in lynx_28g_lane_set_sgmii()
272 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK); in lynx_28g_lane_set_sgmii()
276 lynx_28g_lane_set_pll(lane, pll); in lynx_28g_lane_set_sgmii()
278 /* Choose the portion of clock net to be used on this lane */ in lynx_28g_lane_set_sgmii()
279 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII); in lynx_28g_lane_set_sgmii()
282 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK); in lynx_28g_lane_set_sgmii()
285 iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id)); in lynx_28g_lane_set_sgmii()
286 iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); in lynx_28g_lane_set_sgmii()
287 iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id)); in lynx_28g_lane_set_sgmii()
288 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); in lynx_28g_lane_set_sgmii()
289 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id)); in lynx_28g_lane_set_sgmii()
290 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); in lynx_28g_lane_set_sgmii()
293 static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) in lynx_28g_lane_set_10gbaser() argument
295 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_10gbaser()
296 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_lane_set_10gbaser()
299 lynx_28g_cleanup_lane(lane); in lynx_28g_lane_set_10gbaser()
301 /* Enable the SXGMII lane */ in lynx_28g_lane_set_10gbaser()
307 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK); in lynx_28g_lane_set_10gbaser()
308 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK); in lynx_28g_lane_set_10gbaser()
312 lynx_28g_lane_set_pll(lane, pll); in lynx_28g_lane_set_10gbaser()
314 /* Choose the portion of clock net to be used on this lane */ in lynx_28g_lane_set_10gbaser()
315 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER); in lynx_28g_lane_set_10gbaser()
318 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); in lynx_28g_lane_set_10gbaser()
321 iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id)); in lynx_28g_lane_set_10gbaser()
322 iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); in lynx_28g_lane_set_10gbaser()
323 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id)); in lynx_28g_lane_set_10gbaser()
324 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); in lynx_28g_lane_set_10gbaser()
325 iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id)); in lynx_28g_lane_set_10gbaser()
326 iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); in lynx_28g_lane_set_10gbaser()
331 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_power_off() local
334 if (!lane->powered_up) in lynx_28g_power_off()
338 lynx_28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ); in lynx_28g_power_off()
339 lynx_28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ); in lynx_28g_power_off()
343 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); in lynx_28g_power_off()
344 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_power_off()
348 lane->powered_up = false; in lynx_28g_power_off()
355 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_power_on() local
358 if (lane->powered_up) in lynx_28g_power_on()
361 /* Issue a reset request on the lane */ in lynx_28g_power_on()
362 lynx_28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ); in lynx_28g_power_on()
363 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ); in lynx_28g_power_on()
367 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); in lynx_28g_power_on()
368 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_power_on()
372 lane->powered_up = true; in lynx_28g_power_on()
379 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_set_mode() local
380 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_set_mode()
381 int powered_up = lane->powered_up; in lynx_28g_set_mode()
385 return -EOPNOTSUPP; in lynx_28g_set_mode()
387 if (lane->interface == PHY_INTERFACE_MODE_NA) in lynx_28g_set_mode()
388 return -EOPNOTSUPP; in lynx_28g_set_mode()
391 return -EOPNOTSUPP; in lynx_28g_set_mode()
393 /* If the lane is powered up, put the lane into the halt state while in lynx_28g_set_mode()
402 lynx_28g_lane_set_sgmii(lane); in lynx_28g_set_mode()
405 lynx_28g_lane_set_10gbaser(lane); in lynx_28g_set_mode()
408 err = -EOPNOTSUPP; in lynx_28g_set_mode()
412 lane->interface = submode; in lynx_28g_set_mode()
415 /* Power up the lane if necessary */ in lynx_28g_set_mode()
425 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_validate() local
426 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_validate()
429 return -EOPNOTSUPP; in lynx_28g_validate()
432 return -EOPNOTSUPP; in lynx_28g_validate()
439 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_init() local
441 /* Mark the fact that the lane was init */ in lynx_28g_init()
442 lane->init = true; in lynx_28g_init()
444 /* SerDes lanes are powered on at boot time. Any lane that is managed in lynx_28g_init()
445 * by this driver will get powered down at init time aka at dpaa2-eth in lynx_28g_init()
448 lane->powered_up = true; in lynx_28g_init()
469 pll = &priv->pll[i]; in lynx_28g_pll_read_configuration()
470 pll->priv = priv; in lynx_28g_pll_read_configuration()
471 pll->id = i; in lynx_28g_pll_read_configuration()
473 pll->rstctl = lynx_28g_pll_read(pll, PLLnRSTCTL); in lynx_28g_pll_read_configuration()
474 pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0); in lynx_28g_pll_read_configuration()
475 pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1); in lynx_28g_pll_read_configuration()
477 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_read_configuration()
480 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_pll_read_configuration()
484 __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported); in lynx_28g_pll_read_configuration()
485 __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported); in lynx_28g_pll_read_configuration()
489 __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported); in lynx_28g_pll_read_configuration()
503 struct lynx_28g_lane *lane; in lynx_28g_cdr_lock_check() local
508 lane = &priv->lane[i]; in lynx_28g_cdr_lock_check()
510 if (!lane->init) in lynx_28g_cdr_lock_check()
513 if (!lane->powered_up) in lynx_28g_cdr_lock_check()
516 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_cdr_lock_check()
518 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ); in lynx_28g_cdr_lock_check()
520 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_cdr_lock_check()
524 queue_delayed_work(system_power_efficient_wq, &priv->cdr_check, in lynx_28g_cdr_lock_check()
528 static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane) in lynx_28g_lane_read_configuration() argument
532 pss = lynx_28g_lane_read(lane, LNaPSS); in lynx_28g_lane_read_configuration()
536 lane->interface = PHY_INTERFACE_MODE_SGMII; in lynx_28g_lane_read_configuration()
539 lane->interface = PHY_INTERFACE_MODE_10GBASER; in lynx_28g_lane_read_configuration()
542 lane->interface = PHY_INTERFACE_MODE_NA; in lynx_28g_lane_read_configuration()
550 int idx = args->args[0]; in lynx_28g_xlate()
553 return ERR_PTR(-EINVAL); in lynx_28g_xlate()
555 return priv->lane[idx].phy; in lynx_28g_xlate()
560 struct device *dev = &pdev->dev; in lynx_28g_probe()
565 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in lynx_28g_probe()
567 return -ENOMEM; in lynx_28g_probe()
568 priv->dev = &pdev->dev; in lynx_28g_probe()
570 priv->base = devm_platform_ioremap_resource(pdev, 0); in lynx_28g_probe()
571 if (IS_ERR(priv->base)) in lynx_28g_probe()
572 return PTR_ERR(priv->base); in lynx_28g_probe()
577 struct lynx_28g_lane *lane = &priv->lane[i]; in lynx_28g_probe() local
580 memset(lane, 0, sizeof(*lane)); in lynx_28g_probe()
582 phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops); in lynx_28g_probe()
586 lane->priv = priv; in lynx_28g_probe()
587 lane->phy = phy; in lynx_28g_probe()
588 lane->id = i; in lynx_28g_probe()
589 phy_set_drvdata(phy, lane); in lynx_28g_probe()
590 lynx_28g_lane_read_configuration(lane); in lynx_28g_probe()
595 INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check); in lynx_28g_probe()
597 queue_delayed_work(system_power_efficient_wq, &priv->cdr_check, in lynx_28g_probe()
600 dev_set_drvdata(&pdev->dev, priv); in lynx_28g_probe()
601 provider = devm_of_phy_provider_register(&pdev->dev, lynx_28g_xlate); in lynx_28g_probe()
607 { .compatible = "fsl,lynx-28g" },
615 .name = "lynx-28g",