1 // SPDX-License-Identifier: GPL-2.0
5  * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
19 /* Relative to priv->base */
36 #define     MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY	BIT(2)
84 #define     MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN	BIT(2)
107 /* Relative to priv->regmap */
110 #define     MVEBU_COMPHY_CONF1_USB_PCIE		BIT(2)	/* 0: Ethernet/SATA */
128  * A lane is described by the following bitfields:
129  * [ 1- 0]: COMPHY polarity invertion
130  * [ 2- 7]: COMPHY speed
131  * [ 5-11]: COMPHY port index
132  * [12-16]: COMPHY mode
134  * [18-20]: PCIe width (x1, x2, x4)
138 #define COMPHY_FW_SPEED_OFFSET	2
139 #define COMPHY_FW_SPEED_MASK	GENMASK(7, 2)
142 #define COMPHY_FW_SPEED_3125	2
171 #define COMPHY_FW_MODE_2500BASEX	0x3 /* 2500BASE-X */
181 	unsigned lane;  member
189 		.lane = _lane,				\
199 		.lane = _lane,				\
203 		.mux = -1,				\
208 	/* lane 0 */
213 	/* lane 1 */
218 	ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
219 	ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),
220 	/* lane 2 */
221 	ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
222 	ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),
223 	ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
224 	ETH_CONF(2, 0, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI),
225 	ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
226 	GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
227 	GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
228 	GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
229 	/* lane 3 */
236 	/* lane 4 */
246 	ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX),
247 	ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI),
248 	ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
249 	/* lane 5 */
252 	ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
253 	ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),
254 	GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
276 			    unsigned long lane, unsigned long mode)  in mvebu_comphy_smc()  argument
281 	arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);  in mvebu_comphy_smc()
288 		return -EOPNOTSUPP;  in mvebu_comphy_smc()
290 		return -EINVAL;  in mvebu_comphy_smc()
294 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,  in mvebu_comphy_get_mode()  argument
308 		if (conf->lane == lane &&  in mvebu_comphy_get_mode()
309 		    conf->port == port &&  in mvebu_comphy_get_mode()
310 		    conf->mode == mode &&  in mvebu_comphy_get_mode()
311 		    (conf->submode == submode || ignore_submode))  in mvebu_comphy_get_mode()
316 		return -EINVAL;  in mvebu_comphy_get_mode()
319 		return conf->fw_mode;  in mvebu_comphy_get_mode()
321 		return conf->mux;  in mvebu_comphy_get_mode()
324 static inline int mvebu_comphy_get_mux(int lane, int port,  in mvebu_comphy_get_mux()  argument
327 	return mvebu_comphy_get_mode(false, lane, port, mode, submode);  in mvebu_comphy_get_mux()
330 static inline int mvebu_comphy_get_fw_mode(int lane, int port,  in mvebu_comphy_get_fw_mode()  argument
333 	return mvebu_comphy_get_mode(true, lane, port, mode, submode);  in mvebu_comphy_get_fw_mode()
336 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)  in mvebu_comphy_ethernet_init_reset()  argument
338 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_ethernet_init_reset()
341 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
344 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
347 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
356 	switch (lane->submode) {  in mvebu_comphy_ethernet_init_reset()
377 		dev_err(priv->dev,  in mvebu_comphy_ethernet_init_reset()
378 			"unsupported comphy submode (%d) on lane %d\n",  in mvebu_comphy_ethernet_init_reset()
379 			lane->submode,  in mvebu_comphy_ethernet_init_reset()
380 			lane->id);  in mvebu_comphy_ethernet_init_reset()
381 		return -ENOTSUPP;  in mvebu_comphy_ethernet_init_reset()
384 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
386 	if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {  in mvebu_comphy_ethernet_init_reset()
387 		regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val);  in mvebu_comphy_ethernet_init_reset()
389 		switch (lane->id) {  in mvebu_comphy_ethernet_init_reset()
390 		case 2:  in mvebu_comphy_ethernet_init_reset()
399 			dev_err(priv->dev,  in mvebu_comphy_ethernet_init_reset()
400 				"RXAUI is not supported on comphy lane %d\n",  in mvebu_comphy_ethernet_init_reset()
401 				lane->id);  in mvebu_comphy_ethernet_init_reset()
402 			return -EINVAL;  in mvebu_comphy_ethernet_init_reset()
405 		regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val);  in mvebu_comphy_ethernet_init_reset()
409 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
413 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
415 	/* de-assert reset */  in mvebu_comphy_ethernet_init_reset()
416 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
419 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
425 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
427 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
430 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
432 	if (lane->submode == PHY_INTERFACE_MODE_10GBASER)  in mvebu_comphy_ethernet_init_reset()
434 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
437 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
442 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
444 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
447 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
452 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)  in mvebu_comphy_init_plls()  argument
454 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_init_plls()
458 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
462 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
465 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
472 		return -ETIMEDOUT;  in mvebu_comphy_init_plls()
475 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
477 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
480 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
484 		return -ETIMEDOUT;  in mvebu_comphy_init_plls()
486 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
488 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
495 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_sgmii()  local
496 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_sgmii()
500 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_sgmii()
504 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
507 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
509 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
511 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
513 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_set_mode_sgmii()
516 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_set_mode_sgmii()
518 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
521 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
523 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_sgmii()
528 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_rxaui()  local
529 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_rxaui()
533 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_rxaui()
537 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
540 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
542 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
544 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
546 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
548 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
550 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
552 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
554 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
557 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
559 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
565 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
567 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
569 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
571 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
574 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
576 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_rxaui()
581 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_10gbaser()  local
582 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_10gbaser()
586 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_10gbaser()
590 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
593 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
595 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
597 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
600 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
602 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
604 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
606 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
609 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
611 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
613 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
618 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
620 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
623 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
625 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
628 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
631 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
635 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
637 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
639 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
641 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
651 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
653 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
655 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
657 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
660 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
662 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
664 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
667 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
670 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
673 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
675 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
677 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
680 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
682 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
684 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
686 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
689 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
691 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
694 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
696 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
698 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
700 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
702 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
704 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
708 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
710 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
713 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
716 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
718 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_10gbaser()
723 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on_legacy()  local
724 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on_legacy()
728 	mux = mvebu_comphy_get_mux(lane->id, lane->port,  in mvebu_comphy_power_on_legacy()
729 				   lane->mode, lane->submode);  in mvebu_comphy_power_on_legacy()
731 		return -ENOTSUPP;  in mvebu_comphy_power_on_legacy()
733 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);  in mvebu_comphy_power_on_legacy()
734 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_on_legacy()
735 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);  in mvebu_comphy_power_on_legacy()
737 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);  in mvebu_comphy_power_on_legacy()
738 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_on_legacy()
739 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);  in mvebu_comphy_power_on_legacy()
740 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);  in mvebu_comphy_power_on_legacy()
742 	switch (lane->submode) {  in mvebu_comphy_power_on_legacy()
754 		return -ENOTSUPP;  in mvebu_comphy_power_on_legacy()
758 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
760 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
767 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on()  local
768 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on()
773 	fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,  in mvebu_comphy_power_on()
774 					   lane->mode, lane->submode);  in mvebu_comphy_power_on()
779 	switch (lane->mode) {  in mvebu_comphy_power_on()
781 		switch (lane->submode) {  in mvebu_comphy_power_on()
783 			dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",  in mvebu_comphy_power_on()
784 				lane->id);  in mvebu_comphy_power_on()
788 			dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",  in mvebu_comphy_power_on()
789 				lane->id);  in mvebu_comphy_power_on()
793 			dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",  in mvebu_comphy_power_on()
794 				lane->id);  in mvebu_comphy_power_on()
798 			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",  in mvebu_comphy_power_on()
799 				lane->id);  in mvebu_comphy_power_on()
803 			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",  in mvebu_comphy_power_on()
804 				lane->id);  in mvebu_comphy_power_on()
808 			dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",  in mvebu_comphy_power_on()
809 				lane->submode);  in mvebu_comphy_power_on()
810 			return -ENOTSUPP;  in mvebu_comphy_power_on()
812 		fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);  in mvebu_comphy_power_on()
816 		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);  in mvebu_comphy_power_on()
817 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
820 		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);  in mvebu_comphy_power_on()
821 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
824 		dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,  in mvebu_comphy_power_on()
825 			lane->submode);  in mvebu_comphy_power_on()
826 		fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,  in mvebu_comphy_power_on()
827 						lane->submode);  in mvebu_comphy_power_on()
830 		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);  in mvebu_comphy_power_on()
831 		return -ENOTSUPP;  in mvebu_comphy_power_on()
834 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,  in mvebu_comphy_power_on()
839 	if (ret == -EOPNOTSUPP)  in mvebu_comphy_power_on()
840 		dev_err(priv->dev,  in mvebu_comphy_power_on()
843 	dev_warn(priv->dev,  in mvebu_comphy_power_on()
845 		 lane->id, lane->mode, ret);  in mvebu_comphy_power_on()
855 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode()  local
860 	if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)  in mvebu_comphy_set_mode()
861 		return -EINVAL;  in mvebu_comphy_set_mode()
863 	lane->mode = mode;  in mvebu_comphy_set_mode()
864 	lane->submode = submode;  in mvebu_comphy_set_mode()
867 	if (mode == PHY_MODE_PCIE && !lane->submode)  in mvebu_comphy_set_mode()
868 		lane->submode = 1;  in mvebu_comphy_set_mode()
875 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off_legacy()  local
876 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off_legacy()
879 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
883 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
885 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);  in mvebu_comphy_power_off_legacy()
886 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_off_legacy()
887 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);  in mvebu_comphy_power_off_legacy()
889 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);  in mvebu_comphy_power_off_legacy()
890 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_off_legacy()
891 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);  in mvebu_comphy_power_off_legacy()
898 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off()  local
899 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off()
902 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,  in mvebu_comphy_power_off()
903 			       lane->id, 0);  in mvebu_comphy_power_off()
921 	struct mvebu_comphy_lane *lane;  in mvebu_comphy_xlate()  local
924 	if (WARN_ON(args->args[0] >= MVEBU_COMPHY_PORTS))  in mvebu_comphy_xlate()
925 		return ERR_PTR(-EINVAL);  in mvebu_comphy_xlate()
931 	lane = phy_get_drvdata(phy);  in mvebu_comphy_xlate()
932 	lane->port = args->args[0];  in mvebu_comphy_xlate()
941 	priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");  in mvebu_comphy_init_clks()
942 	if (IS_ERR(priv->mg_domain_clk))  in mvebu_comphy_init_clks()
943 		return PTR_ERR(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
945 	ret = clk_prepare_enable(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
949 	priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");  in mvebu_comphy_init_clks()
950 	if (IS_ERR(priv->mg_core_clk)) {  in mvebu_comphy_init_clks()
951 		ret = PTR_ERR(priv->mg_core_clk);  in mvebu_comphy_init_clks()
955 	ret = clk_prepare_enable(priv->mg_core_clk);  in mvebu_comphy_init_clks()
959 	priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");  in mvebu_comphy_init_clks()
960 	if (IS_ERR(priv->axi_clk)) {  in mvebu_comphy_init_clks()
961 		ret = PTR_ERR(priv->axi_clk);  in mvebu_comphy_init_clks()
965 	ret = clk_prepare_enable(priv->axi_clk);  in mvebu_comphy_init_clks()
972 	clk_disable_unprepare(priv->mg_core_clk);  in mvebu_comphy_init_clks()
975 	clk_disable_unprepare(priv->mg_domain_clk);  in mvebu_comphy_init_clks()
977 	priv->mg_domain_clk = NULL;  in mvebu_comphy_init_clks()
978 	priv->mg_core_clk = NULL;  in mvebu_comphy_init_clks()
979 	priv->axi_clk = NULL;  in mvebu_comphy_init_clks()
986 	if (priv->axi_clk)  in mvebu_comphy_disable_unprepare_clks()
987 		clk_disable_unprepare(priv->axi_clk);  in mvebu_comphy_disable_unprepare_clks()
989 	if (priv->mg_core_clk)  in mvebu_comphy_disable_unprepare_clks()
990 		clk_disable_unprepare(priv->mg_core_clk);  in mvebu_comphy_disable_unprepare_clks()
992 	if (priv->mg_domain_clk)  in mvebu_comphy_disable_unprepare_clks()
993 		clk_disable_unprepare(priv->mg_domain_clk);  in mvebu_comphy_disable_unprepare_clks()
1004 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in mvebu_comphy_probe()
1006 		return -ENOMEM;  in mvebu_comphy_probe()
1008 	priv->dev = &pdev->dev;  in mvebu_comphy_probe()
1009 	priv->regmap =  in mvebu_comphy_probe()
1010 		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,  in mvebu_comphy_probe()
1011 						"marvell,system-controller");  in mvebu_comphy_probe()
1012 	if (IS_ERR(priv->regmap))  in mvebu_comphy_probe()
1013 		return PTR_ERR(priv->regmap);  in mvebu_comphy_probe()
1015 	priv->base = devm_ioremap_resource(&pdev->dev, res);  in mvebu_comphy_probe()
1016 	if (IS_ERR(priv->base))  in mvebu_comphy_probe()
1017 		return PTR_ERR(priv->base);  in mvebu_comphy_probe()
1025 		if (ret == -EPROBE_DEFER)  in mvebu_comphy_probe()
1027 		dev_warn(&pdev->dev, "cannot initialize clocks\n");  in mvebu_comphy_probe()
1034 	priv->cp_phys = res->start;  in mvebu_comphy_probe()
1036 	for_each_available_child_of_node(pdev->dev.of_node, child) {  in mvebu_comphy_probe()
1037 		struct mvebu_comphy_lane *lane;  in mvebu_comphy_probe()  local
1043 			dev_err(&pdev->dev, "missing 'reg' property (%d)\n",  in mvebu_comphy_probe()
1049 			dev_err(&pdev->dev, "invalid 'reg' property\n");  in mvebu_comphy_probe()
1053 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);  in mvebu_comphy_probe()
1054 		if (!lane) {  in mvebu_comphy_probe()
1056 			ret = -ENOMEM;  in mvebu_comphy_probe()
1060 		phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);  in mvebu_comphy_probe()
1067 		lane->priv = priv;  in mvebu_comphy_probe()
1068 		lane->mode = PHY_MODE_INVALID;  in mvebu_comphy_probe()
1069 		lane->submode = PHY_INTERFACE_MODE_NA;  in mvebu_comphy_probe()
1070 		lane->id = val;  in mvebu_comphy_probe()
1071 		lane->port = -1;  in mvebu_comphy_probe()
1072 		phy_set_drvdata(phy, lane);  in mvebu_comphy_probe()
1078 		 * reasons we cannot de-configure the COMPHY without being sure  in mvebu_comphy_probe()
1079 		 * that the firmware is up-to-date and fully-featured.  in mvebu_comphy_probe()
1083 	dev_set_drvdata(&pdev->dev, priv);  in mvebu_comphy_probe()
1084 	provider = devm_of_phy_provider_register(&pdev->dev,  in mvebu_comphy_probe()
1096 	{ .compatible = "marvell,comphy-cp110" },
1104 		.name = "mvebu-comphy",
1110 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");