Lines Matching +full:2 +full:- +full:lane
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
29 '#clock-cells':
35 - description: Sierra PHY reset.
36 - description: Sierra APB reset. This is optional.
38 reset-names:
41 - const: sierra_reset
42 - const: sierra_apb
49 reg-names:
53 minItems: 2
56 clock-names:
57 minItems: 2
59 - const: cmn_refclk_dig_div
60 - const: cmn_refclk1_dig_div
61 - const: pll0_refclk
62 - const: pll1_refclk
64 assigned-clocks:
66 maxItems: 2
68 assigned-clock-parents:
70 maxItems: 2
76 configured by hardware. If not present, all sub-node optional properties
80 '^phy@[0-9a-f]$':
83 Each group of PHY lanes with a single master lane should be represented as
84 a sub-node. Note that the actual configuration of each lane is determined
89 The master lane number. This is the lowest numbered lane in the lane group.
97 Contains list of resets, one per lane, to get all the link lanes out of reset.
99 "#phy-cells":
102 cdns,phy-type:
105 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
107 enum: [2, 4]
109 cdns,num-lanes:
116 cdns,ssc-mode:
120 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
122 enum: [0, 1, 2]
126 - reg
127 - resets
128 - "#phy-cells"
133 - compatible
134 - "#address-cells"
135 - "#size-cells"
136 - reg
137 - resets
138 - reset-names
143 - |
144 #include <dt-bindings/phy/phy.h>
147 #address-cells = <2>;
148 #size-cells = <2>;
150 sierra-phy@fd240000 {
151 compatible = "cdns,sierra-phy-t0";
154 reset-names = "sierra_reset", "sierra_apb";
156 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
157 #address-cells = <1>;
158 #size-cells = <0>;
161 resets = <&phyrst 2>;
162 cdns,num-lanes = <2>;
163 #phy-cells = <0>;
164 cdns,phy-type = <PHY_TYPE_PCIE>;
166 pcie0_phy1: phy@2 {
167 reg = <2>;
169 cdns,num-lanes = <1>;
170 #phy-cells = <0>;
171 cdns,phy-type = <PHY_TYPE_PCIE>;