Lines Matching +full:2 +full:- +full:lane
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
52 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
61 a device is partitioned into multiple data busses, e.g. 16-bit input port
62 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
63 and data-shift properties can be used to assign physical data lines to each
67 --------------------------------
71 endpoint nodes for the device, including unit-addresses and reg properties
75 - $ref: /schemas/graph.yaml#/$defs/endpoint-base
78 slave-mode:
87 bus-type:
90 - 1 # MIPI CSI-2 C-PHY
91 - 2 # MIPI CSI1
92 - 3 # CCP2
93 - 4 # MIPI CSI-2 D-PHY
94 - 5 # Parallel
95 - 6 # BT.656
96 - 7 # DPI
100 bus-width:
106 data-shift:
110 On the parallel data busses, if bus-width is used to specify the number of
111 data lines, data-shift can be used to specify which data lines are used,
112 e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
114 hsync-active:
120 vsync-active:
128 data-active:
134 data-enable-active:
140 field-even-active:
146 pclk-sample:
152 sync-on-green-active:
156 Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively.
158 data-lanes:
159 $ref: /schemas/types.yaml#/definitions/uint32-array
163 # Assume up to 9 physical lane indices
166 An array of physical data lane indexes. Position of an entry determines
167 the logical lane number, while the value of an entry indicates physical
168 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
169 assuming the clock lane is on hardware lane 0. If the hardware does not
170 support lane reordering, monotonically incremented values shall be used
172 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
174 clock-lanes:
176 # Assume up to 9 physical lane indices
179 Physical clock lane index. Position of an entry determines the logical
180 lane number, while the value of an entry indicates physical lane, e.g. for
181 a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
182 clock lane on hardware lane 0. This property is valid for serial busses
183 only (e.g. MIPI CSI-2).
185 clock-noncontinuous:
188 Allow MIPI CSI-2 non-continuous clock mode.
190 link-frequencies:
191 $ref: /schemas/types.yaml#/definitions/uint64-array
193 Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
194 actual frequency of the bus, not bits per clock per lane value. An array
195 of 64-bit unsigned integers.
197 lane-polarities:
198 $ref: /schemas/types.yaml#/definitions/uint32-array
204 An array of polarities of the lanes starting from the clock lane and
205 followed by the data lanes in the same order as in data-lanes. Valid
207 the combined length of data-lanes and clock-lanes properties. If the
208 lane-polarities property is omitted, the value must be interpreted as 0