1 // SPDX-License-Identifier: GPL-2.0
11  * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
39  * When accessing common PHY lane registers directly, we need to shift by 1,
40  * since the registers are 16-bit.
68 #define SPEED_PLL_MASK			GENMASK(7, 2)
137 #define GEN2_TX_DATA_DLY_DEFT		FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
155 #define MODE_MARGIN_OVERRIDE		BIT(2)
160 #define BUNDLE_PERIOD_SCALE_MASK	GENMASK(3, 2)
174  * This register is not from PHY lane register space. It only exists in the
175  * indirect register space, before the actual PHY lane 2 registers. So the
183 #define COMPHY_PHY_REG(lane, reg)	(((1 - (lane)) * 0x28) + ((reg) & 0x3f))  argument
213 #define PHY_PLL_READY_RX_BIT		BIT(2)
226 	unsigned int lane;  member
233 		.lane = _lane,						\
245 	/* lane 0 */
250 	/* lane 1 */
255 	/* lane 2 */
256 	MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA),
257 	MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS),
299 	/* 0       1       2       3       4       5       6       7 */
300 	/*-----------------------------------------------------------*/
386 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
391 	       priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR);  in comphy_set_indirect()
392 	comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA,  in comphy_set_indirect()
396 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,  in comphy_lane_reg_set()  argument
399 	if (lane->id == 2) {  in comphy_lane_reg_set()
400 		/* lane 2 PHY registers are accessed indirectly */  in comphy_lane_reg_set()
401 		comphy_set_indirect(lane->priv,  in comphy_lane_reg_set()
405 		void __iomem *base = lane->id == 1 ?  in comphy_lane_reg_set()
406 				     lane->priv->lane1_phy_regs :  in comphy_lane_reg_set()
407 				     lane->priv->lane0_phy_regs;  in comphy_lane_reg_set()
414 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,  in comphy_lane_reg_poll()  argument
420 	if (lane->id == 2) {  in comphy_lane_reg_poll()
423 		/* lane 2 PHY registers are accessed indirectly */  in comphy_lane_reg_poll()
425 		       lane->priv->lane2_phy_indirect +  in comphy_lane_reg_poll()
428 		ret = readl_poll_timeout(lane->priv->lane2_phy_indirect +  in comphy_lane_reg_poll()
433 		void __iomem *base = lane->id == 1 ?  in comphy_lane_reg_poll()
434 				     lane->priv->lane1_phy_regs :  in comphy_lane_reg_poll()
435 				     lane->priv->lane0_phy_regs;  in comphy_lane_reg_poll()
446 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,  in comphy_periph_reg_set()  argument
449 	comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),  in comphy_periph_reg_set()
453 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,  in comphy_periph_reg_poll()  argument
459 	return readl_poll_timeout(lane->priv->comphy_regs +  in comphy_periph_reg_poll()
460 				  COMPHY_PHY_REG(lane->id, reg),  in comphy_periph_reg_poll()
467 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_set_phy_selector()  argument
472 	switch (lane->mode) {  in mvebu_a3700_comphy_set_phy_selector()
475 		if (lane->id == 2)  in mvebu_a3700_comphy_set_phy_selector()
482 		if (lane->id == 0)  in mvebu_a3700_comphy_set_phy_selector()
484 		else if (lane->id == 1)  in mvebu_a3700_comphy_set_phy_selector()
491 		if (lane->id == 2)  in mvebu_a3700_comphy_set_phy_selector()
493 		else if (lane->id == 0)  in mvebu_a3700_comphy_set_phy_selector()
501 		if (lane->id == 1)  in mvebu_a3700_comphy_set_phy_selector()
511 	spin_lock_irqsave(&lane->priv->lock, flags);  in mvebu_a3700_comphy_set_phy_selector()
513 	old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);  in mvebu_a3700_comphy_set_phy_selector()
515 	writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);  in mvebu_a3700_comphy_set_phy_selector()
517 	spin_unlock_irqrestore(&lane->priv->lock, flags);  in mvebu_a3700_comphy_set_phy_selector()
519 	dev_dbg(lane->dev,  in mvebu_a3700_comphy_set_phy_selector()
520 		"COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n",  in mvebu_a3700_comphy_set_phy_selector()
521 		lane->id, lane->mode, old, new);  in mvebu_a3700_comphy_set_phy_selector()
525 	dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id,  in mvebu_a3700_comphy_set_phy_selector()
526 		lane->mode);  in mvebu_a3700_comphy_set_phy_selector()
527 	return -EINVAL;  in mvebu_a3700_comphy_set_phy_selector()
531 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_sata_power_on()  argument
537 	ret = mvebu_a3700_comphy_set_phy_selector(lane);  in mvebu_a3700_comphy_sata_power_on()
542 	comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,  in mvebu_a3700_comphy_sata_power_on()
547 	if (lane->invert_tx)  in mvebu_a3700_comphy_sata_power_on()
549 	if (lane->invert_rx)  in mvebu_a3700_comphy_sata_power_on()
552 	comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);  in mvebu_a3700_comphy_sata_power_on()
554 	/* 1. Select 40-bit data width */  in mvebu_a3700_comphy_sata_power_on()
555 	comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,  in mvebu_a3700_comphy_sata_power_on()
558 	/* 2. Select reference clock(25M) and PHY mode (SATA) */  in mvebu_a3700_comphy_sata_power_on()
559 	if (lane->priv->xtal_is_40m)  in mvebu_a3700_comphy_sata_power_on()
566 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);  in mvebu_a3700_comphy_sata_power_on()
569 	comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,  in mvebu_a3700_comphy_sata_power_on()
573 	comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,  in mvebu_a3700_comphy_sata_power_on()
576 	/* 5. Set vendor-specific configuration (It is done in sata driver) */  in mvebu_a3700_comphy_sata_power_on()
577 	/* XXX: in U-Boot below sequence was executed in this place, in Linux  in mvebu_a3700_comphy_sata_power_on()
578 	 * not.  Now it is done only in U-Boot before this comphy  in mvebu_a3700_comphy_sata_power_on()
579 	 * initialization - tests shows that it works ok, but in case of any  in mvebu_a3700_comphy_sata_power_on()
589 	ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,  in mvebu_a3700_comphy_sata_power_on()
593 		dev_err(lane->dev, "Failed to lock SATA PLL\n");  in mvebu_a3700_comphy_sata_power_on()
598 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,  in comphy_gbe_phy_init()  argument
622 		comphy_lane_reg_set(lane, addr, val, 0xFFFF);  in comphy_gbe_phy_init()
627 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_ethernet_power_on()  argument
633 	ret = mvebu_a3700_comphy_set_phy_selector(lane);  in mvebu_a3700_comphy_ethernet_power_on()
639 	 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep  in mvebu_a3700_comphy_ethernet_power_on()
646 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
651 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
657 	switch (lane->submode) {  in mvebu_a3700_comphy_ethernet_power_on()
664 		/* 2500Base-X, SerDes speed 3.125G */  in mvebu_a3700_comphy_ethernet_power_on()
669 		dev_err(lane->dev,  in mvebu_a3700_comphy_ethernet_power_on()
670 			"unsupported phy speed %d on comphy lane%d\n",  in mvebu_a3700_comphy_ethernet_power_on()
671 			lane->submode, lane->id);  in mvebu_a3700_comphy_ethernet_power_on()
672 		return -EINVAL;  in mvebu_a3700_comphy_ethernet_power_on()
676 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
687 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
695 	comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
701 	if (lane->priv->xtal_is_40m)  in mvebu_a3700_comphy_ethernet_power_on()
707 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
723 	comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
737 	 * the related GEN table during real chip bring-up. We only required to  in mvebu_a3700_comphy_ethernet_power_on()
742 	dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n",  in mvebu_a3700_comphy_ethernet_power_on()
743 		lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G");  in mvebu_a3700_comphy_ethernet_power_on()
744 	if (lane->priv->xtal_is_40m)  in mvebu_a3700_comphy_ethernet_power_on()
745 		comphy_gbe_phy_init(lane,  in mvebu_a3700_comphy_ethernet_power_on()
746 				    lane->submode != PHY_INTERFACE_MODE_2500BASEX);  in mvebu_a3700_comphy_ethernet_power_on()
752 	if (lane->invert_tx)  in mvebu_a3700_comphy_ethernet_power_on()
754 	if (lane->invert_rx)  in mvebu_a3700_comphy_ethernet_power_on()
757 	comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
767 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);  in mvebu_a3700_comphy_ethernet_power_on()
773 	ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,  in mvebu_a3700_comphy_ethernet_power_on()
778 		dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",  in mvebu_a3700_comphy_ethernet_power_on()
779 			lane->id);  in mvebu_a3700_comphy_ethernet_power_on()
786 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);  in mvebu_a3700_comphy_ethernet_power_on()
795 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1,  in mvebu_a3700_comphy_ethernet_power_on()
798 	ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,  in mvebu_a3700_comphy_ethernet_power_on()
803 		dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",  in mvebu_a3700_comphy_ethernet_power_on()
804 			lane->id);  in mvebu_a3700_comphy_ethernet_power_on()
808 	ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,  in mvebu_a3700_comphy_ethernet_power_on()
812 		dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n",  in mvebu_a3700_comphy_ethernet_power_on()
813 			lane->id);  in mvebu_a3700_comphy_ethernet_power_on()
819 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_usb3_power_on()  argument
825 	ret = mvebu_a3700_comphy_set_phy_selector(lane);  in mvebu_a3700_comphy_usb3_power_on()
835 	 * 1. Set PRD_TXDEEMPH (3.5db de-emph)  in mvebu_a3700_comphy_usb3_power_on()
840 	comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
843 	 * 2. Set BIT0: enable transmitter in high impedance mode  in mvebu_a3700_comphy_usb3_power_on()
844 	 *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency  in mvebu_a3700_comphy_usb3_power_on()
846 	 *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db  in mvebu_a3700_comphy_usb3_power_on()
852 	comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
857 	comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,  in mvebu_a3700_comphy_usb3_power_on()
862 	 *    Use margining signals from lane configuration  in mvebu_a3700_comphy_usb3_power_on()
864 	comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,  in mvebu_a3700_comphy_usb3_power_on()
868 	 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles  in mvebu_a3700_comphy_usb3_power_on()
874 	comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
879 	comphy_lane_reg_set(lane, COMPHY_GEN2_SET2,  in mvebu_a3700_comphy_usb3_power_on()
889 	comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
895 	if (lane->priv->xtal_is_40m) {  in mvebu_a3700_comphy_usb3_power_on()
908 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
913 	comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
918 	comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,  in mvebu_a3700_comphy_usb3_power_on()
924 	comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);  in mvebu_a3700_comphy_usb3_power_on()
927 	 * 11. Set 20-bit data width  in mvebu_a3700_comphy_usb3_power_on()
929 	comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,  in mvebu_a3700_comphy_usb3_power_on()
937 	comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
943 	if (lane->invert_tx)  in mvebu_a3700_comphy_usb3_power_on()
945 	if (lane->invert_rx)  in mvebu_a3700_comphy_usb3_power_on()
948 	comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
953 	comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,  in mvebu_a3700_comphy_usb3_power_on()
959 	comphy_lane_reg_set(lane, COMPHY_GEN2_SET3,  in mvebu_a3700_comphy_usb3_power_on()
967 	comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);  in mvebu_a3700_comphy_usb3_power_on()
972 	ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,  in mvebu_a3700_comphy_usb3_power_on()
975 		dev_err(lane->dev, "Failed to lock USB3 PLL\n");  in mvebu_a3700_comphy_usb3_power_on()
981 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_pcie_power_on()  argument
987 	ret = mvebu_a3700_comphy_set_phy_selector(lane);  in mvebu_a3700_comphy_pcie_power_on()
992 	comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,  in mvebu_a3700_comphy_pcie_power_on()
995 	/* 2. Select 20 bit SERDES interface. */  in mvebu_a3700_comphy_pcie_power_on()
996 	comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,  in mvebu_a3700_comphy_pcie_power_on()
1000 	comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,  in mvebu_a3700_comphy_pcie_power_on()
1007 	comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);  in mvebu_a3700_comphy_pcie_power_on()
1010 	comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,  in mvebu_a3700_comphy_pcie_power_on()
1016 	comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);  in mvebu_a3700_comphy_pcie_power_on()
1020 	 * PCI-E driver  in mvebu_a3700_comphy_pcie_power_on()
1028 	if (lane->priv->xtal_is_40m)  in mvebu_a3700_comphy_pcie_power_on()
1036 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);  in mvebu_a3700_comphy_pcie_power_on()
1039 	comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,  in mvebu_a3700_comphy_pcie_power_on()
1045 	if (lane->invert_tx)  in mvebu_a3700_comphy_pcie_power_on()
1047 	if (lane->invert_rx)  in mvebu_a3700_comphy_pcie_power_on()
1050 	comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);  in mvebu_a3700_comphy_pcie_power_on()
1055 	comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);  in mvebu_a3700_comphy_pcie_power_on()
1060 	ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,  in mvebu_a3700_comphy_pcie_power_on()
1063 		dev_err(lane->dev, "Failed to lock PCIE PLL\n");  in mvebu_a3700_comphy_pcie_power_on()
1069 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_sata_power_off()  argument
1072 	comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,  in mvebu_a3700_comphy_sata_power_off()
1076 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,  in mvebu_a3700_comphy_sata_power_off()
1081 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_ethernet_power_off()  argument
1088 	comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);  in mvebu_a3700_comphy_ethernet_power_off()
1092 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_pcie_power_off()  argument
1095 	comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,  in mvebu_a3700_comphy_pcie_power_off()
1099 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)  in mvebu_a3700_comphy_usb3_power_off()  argument
1107 static bool mvebu_a3700_comphy_check_mode(int lane,  in mvebu_a3700_comphy_check_mode()  argument
1118 		if (mvebu_a3700_comphy_modes[i].lane == lane &&  in mvebu_a3700_comphy_check_mode()
1133 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_a3700_comphy_set_mode()  local
1135 	if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {  in mvebu_a3700_comphy_set_mode()
1136 		dev_err(lane->dev, "invalid COMPHY mode\n");  in mvebu_a3700_comphy_set_mode()
1137 		return -EINVAL;  in mvebu_a3700_comphy_set_mode()
1141 	if (phy->power_count &&  in mvebu_a3700_comphy_set_mode()
1142 	    (lane->mode != mode || lane->submode != submode))  in mvebu_a3700_comphy_set_mode()
1143 		return -EBUSY;  in mvebu_a3700_comphy_set_mode()
1145 	/* Just remember the mode, ->power_on() will do the real setup */  in mvebu_a3700_comphy_set_mode()
1146 	lane->mode = mode;  in mvebu_a3700_comphy_set_mode()
1147 	lane->submode = submode;  in mvebu_a3700_comphy_set_mode()
1154 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_a3700_comphy_power_on()  local
1156 	if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,  in mvebu_a3700_comphy_power_on()
1157 					   lane->submode)) {  in mvebu_a3700_comphy_power_on()
1158 		dev_err(lane->dev, "invalid COMPHY mode\n");  in mvebu_a3700_comphy_power_on()
1159 		return -EINVAL;  in mvebu_a3700_comphy_power_on()
1162 	switch (lane->mode) {  in mvebu_a3700_comphy_power_on()
1164 		dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);  in mvebu_a3700_comphy_power_on()
1165 		return mvebu_a3700_comphy_usb3_power_on(lane);  in mvebu_a3700_comphy_power_on()
1167 		dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);  in mvebu_a3700_comphy_power_on()
1168 		return mvebu_a3700_comphy_sata_power_on(lane);  in mvebu_a3700_comphy_power_on()
1170 		dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id);  in mvebu_a3700_comphy_power_on()
1171 		return mvebu_a3700_comphy_ethernet_power_on(lane);  in mvebu_a3700_comphy_power_on()
1173 		dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);  in mvebu_a3700_comphy_power_on()
1174 		return mvebu_a3700_comphy_pcie_power_on(lane);  in mvebu_a3700_comphy_power_on()
1176 		dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);  in mvebu_a3700_comphy_power_on()
1177 		return -EOPNOTSUPP;  in mvebu_a3700_comphy_power_on()
1183 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_a3700_comphy_power_off()  local
1185 	switch (lane->id) {  in mvebu_a3700_comphy_power_off()
1187 		mvebu_a3700_comphy_usb3_power_off(lane);  in mvebu_a3700_comphy_power_off()
1188 		mvebu_a3700_comphy_ethernet_power_off(lane);  in mvebu_a3700_comphy_power_off()
1191 		mvebu_a3700_comphy_pcie_power_off(lane);  in mvebu_a3700_comphy_power_off()
1192 		mvebu_a3700_comphy_ethernet_power_off(lane);  in mvebu_a3700_comphy_power_off()
1194 	case 2:  in mvebu_a3700_comphy_power_off()
1195 		mvebu_a3700_comphy_usb3_power_off(lane);  in mvebu_a3700_comphy_power_off()
1196 		mvebu_a3700_comphy_sata_power_off(lane);  in mvebu_a3700_comphy_power_off()
1199 		dev_err(lane->dev, "invalid COMPHY mode\n");  in mvebu_a3700_comphy_power_off()
1200 		return -EINVAL;  in mvebu_a3700_comphy_power_off()
1214 	struct mvebu_a3700_comphy_lane *lane;  in mvebu_a3700_comphy_xlate()  local
1222 	lane = phy_get_drvdata(phy);  in mvebu_a3700_comphy_xlate()
1224 	port = args->args[0];  in mvebu_a3700_comphy_xlate()
1225 	if (port != 0 && (port != 1 || lane->id != 0)) {  in mvebu_a3700_comphy_xlate()
1226 		dev_err(lane->dev, "invalid port number %u\n", port);  in mvebu_a3700_comphy_xlate()
1227 		return ERR_PTR(-EINVAL);  in mvebu_a3700_comphy_xlate()
1230 	lane->invert_tx = args->args[1] & BIT(0);  in mvebu_a3700_comphy_xlate()
1231 	lane->invert_rx = args->args[1] & BIT(1);  in mvebu_a3700_comphy_xlate()
1245 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in mvebu_a3700_comphy_probe()
1247 		return -ENOMEM;  in mvebu_a3700_comphy_probe()
1249 	spin_lock_init(&priv->lock);  in mvebu_a3700_comphy_probe()
1252 	priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res);  in mvebu_a3700_comphy_probe()
1253 	if (IS_ERR(priv->comphy_regs))  in mvebu_a3700_comphy_probe()
1254 		return PTR_ERR(priv->comphy_regs);  in mvebu_a3700_comphy_probe()
1258 	priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res);  in mvebu_a3700_comphy_probe()
1259 	if (IS_ERR(priv->lane1_phy_regs))  in mvebu_a3700_comphy_probe()
1260 		return PTR_ERR(priv->lane1_phy_regs);  in mvebu_a3700_comphy_probe()
1264 	priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res);  in mvebu_a3700_comphy_probe()
1265 	if (IS_ERR(priv->lane0_phy_regs))  in mvebu_a3700_comphy_probe()
1266 		return PTR_ERR(priv->lane0_phy_regs);  in mvebu_a3700_comphy_probe()
1270 	priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res);  in mvebu_a3700_comphy_probe()
1271 	if (IS_ERR(priv->lane2_phy_indirect))  in mvebu_a3700_comphy_probe()
1272 		return PTR_ERR(priv->lane2_phy_indirect);  in mvebu_a3700_comphy_probe()
1279 	clk = clk_get(&pdev->dev, "xtal");  in mvebu_a3700_comphy_probe()
1281 		if (PTR_ERR(clk) == -EPROBE_DEFER)  in mvebu_a3700_comphy_probe()
1282 			return -EPROBE_DEFER;  in mvebu_a3700_comphy_probe()
1283 		dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n",  in mvebu_a3700_comphy_probe()
1288 			dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n",  in mvebu_a3700_comphy_probe()
1292 				priv->xtal_is_40m = true;  in mvebu_a3700_comphy_probe()
1298 	dev_set_drvdata(&pdev->dev, priv);  in mvebu_a3700_comphy_probe()
1300 	for_each_available_child_of_node(pdev->dev.of_node, child) {  in mvebu_a3700_comphy_probe()
1301 		struct mvebu_a3700_comphy_lane *lane;  in mvebu_a3700_comphy_probe()  local
1308 			dev_err(&pdev->dev, "missing 'reg' property (%d)\n",  in mvebu_a3700_comphy_probe()
1314 			dev_err(&pdev->dev, "invalid 'reg' property\n");  in mvebu_a3700_comphy_probe()
1318 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);  in mvebu_a3700_comphy_probe()
1319 		if (!lane) {  in mvebu_a3700_comphy_probe()
1321 			return -ENOMEM;  in mvebu_a3700_comphy_probe()
1324 		phy = devm_phy_create(&pdev->dev, child,  in mvebu_a3700_comphy_probe()
1331 		lane->priv = priv;  in mvebu_a3700_comphy_probe()
1332 		lane->dev = &pdev->dev;  in mvebu_a3700_comphy_probe()
1333 		lane->mode = PHY_MODE_INVALID;  in mvebu_a3700_comphy_probe()
1334 		lane->submode = PHY_INTERFACE_MODE_NA;  in mvebu_a3700_comphy_probe()
1335 		lane->id = lane_id;  in mvebu_a3700_comphy_probe()
1336 		lane->invert_tx = false;  in mvebu_a3700_comphy_probe()
1337 		lane->invert_rx = false;  in mvebu_a3700_comphy_probe()
1338 		phy_set_drvdata(phy, lane);  in mvebu_a3700_comphy_probe()
1347 	provider = devm_of_phy_provider_register(&pdev->dev,  in mvebu_a3700_comphy_probe()
1354 	{ .compatible = "marvell,comphy-a3700" },
1362 		.name = "mvebu-a3700-comphy",