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/Linux-v5.10/drivers/net/ethernet/freescale/dpaa2/
Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
25 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
33 DPKG_FULL_FIELD = 2
37 * enum dpkg_extract_type - Enumeration for selecting extraction type
40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
51 * struct dpkg_mask - A structure for defining a single extraction mask
63 #define NH_FLD_ETH_DA BIT(0)
64 #define NH_FLD_ETH_SA BIT(1)
65 #define NH_FLD_ETH_LENGTH BIT(2)
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/Linux-v5.10/include/linux/mfd/abx500/
Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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/Linux-v5.10/drivers/net/dsa/microchip/
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
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Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #define KS_PRIO_S 2
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
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/Linux-v5.10/drivers/staging/comedi/drivers/
Dni_tio_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
[all …]
Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
24 #define NISTC_INTA_ACK_REG 2
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
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/Linux-v5.10/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
56 * Multi-Function GPIO Pin Control.
59 * Multi-Function GPIO Select.
63 * Multi-Function control source.
117 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 2)
119 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2)
175 /* RTL8723 series ------------------------------ */
230 #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */
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/Linux-v5.10/include/linux/mfd/
Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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Dlp873x.h4 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
8 * published by the Free Software Foundation version 2.
76 #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3)
77 #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2)
78 #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1)
79 #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0)
84 #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3)
85 #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2)
86 #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1)
87 #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0)
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/Linux-v5.10/drivers/media/i2c/
Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
125 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
126 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
127 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
128 #define DETECT_5V_B BIT(1) /* 5V present on input B */
129 #define DETECT_5V_A BIT(0) /* 5V present on input A */
132 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
133 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
134 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
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/Linux-v5.10/drivers/clk/sunxi-ng/
Dccu-sun50i-a64.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
44 * the base (2x, 4x and 8x), and one variable divider (the one true
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Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
34 4, 2, /* K */
35 0, 2, /* M */
36 BIT(31), /* gate */
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Dccu-sun8i-r40.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
36 .hw.init = CLK_HW_INIT("pll-cpu",
45 * the base (2x, 4x and 8x), and one variable divider (the one true
[all …]
Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
32 .k = _SUNXI_CCU_MULT(4, 2),
33 .m = _SUNXI_CCU_DIV(0, 2),
34 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 * the base (2x, 4x and 8x), and one variable divider (the one true
[all …]
/Linux-v5.10/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
77 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
81 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
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/Linux-v5.10/drivers/net/wireless/ath/wil6210/
Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
Dtxrx_edma.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
32 #define WIL_RX_EDMA_ERROR_KEY (2) /* Key missing */
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
44 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
58 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2
75 /* Enhanced Rx descriptor - MAC part
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/Linux-v5.10/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-txcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SP_REGISTER_PD BIT(7)
28 #define SP_HDCP_PD BIT(5)
29 #define SP_AUDIO_PD BIT(4)
30 #define SP_VIDEO_PD BIT(3)
31 #define SP_LINK_PD BIT(2)
32 #define SP_TOTAL_PD BIT(1)
36 #define SP_MISC_RST BIT(7)
37 #define SP_VIDCAP_RST BIT(6)
38 #define SP_VIDFIF_RST BIT(5)
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/Linux-v5.10/drivers/staging/vt6656/
Dmac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
16 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
17 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
146 #define I2MCFG_BOUNDCTL BIT(7)
147 #define I2MCFG_WAITCTL BIT(5)
148 #define I2MCFG_SCLOECTL BIT(4)
149 #define I2MCFG_WBUSYCTL BIT(3)
150 #define I2MCFG_NORETRY BIT(2)
151 #define I2MCFG_I2MLDSEQ BIT(1)
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/Linux-v5.10/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
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/Linux-v5.10/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
165 #define DA9062AA_DVC_BUSY_SHIFT 2
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
173 #define DA9062AA_GPI2_SHIFT 2
174 #define DA9062AA_GPI2_MASK BIT(2)
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/Linux-v5.10/drivers/gpu/drm/rcar-du/
Drcar_du_drv.c1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
32 /* -----------------------------------------------------------------------------
37 .gen = 2,
41 .channels_mask = BIT(1) | BIT(0),
47 .possible_crtcs = BIT(1) | BIT(0),
51 .possible_crtcs = BIT(0),
59 .gen = 2,
63 .channels_mask = BIT(1) | BIT(0),
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/Linux-v5.10/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
162 #define DA9150_REVERT_MASK BIT(7)
165 #define DA9150_WKUP_STAT_SHIFT 2
166 #define DA9150_WKUP_STAT_MASK (0x0f << 2)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
[all …]
/Linux-v5.10/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
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/Linux-v5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac4.h1 /* SPDX-License-Identifier: GPL-2.0-only */
54 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
64 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
66 #define GMAC_RXQCTRL_TACPQE BIT(21)
72 #define GMAC_PACKET_FILTER_PR BIT(0)
73 #define GMAC_PACKET_FILTER_HMC BIT(2)
74 #define GMAC_PACKET_FILTER_PM BIT(4)
75 #define GMAC_PACKET_FILTER_PCF BIT(7)
76 #define GMAC_PACKET_FILTER_HPF BIT(10)
77 #define GMAC_PACKET_FILTER_VTFE BIT(16)
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