Lines Matching +full:2 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
36 .hw.init = CLK_HW_INIT("pll-cpu",
45 * the base (2x, 4x and 8x), and one variable divider (the one true
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
68 BIT(31), /* gate */
69 BIT(28), /* lock */
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
78 BIT(24), /* frac enable */
79 BIT(25), /* frac select */
82 BIT(31), /* gate */
83 BIT(28), /* lock */
87 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
91 BIT(24), /* frac enable */
92 BIT(25), /* frac select */
95 BIT(31), /* gate */
96 BIT(28), /* lock */
100 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
103 4, 2, /* K */
104 0, 2, /* M */
105 BIT(31), /* gate */
106 BIT(28), /* lock */
111 .enable = BIT(31),
112 .lock = BIT(28),
114 .k = _SUNXI_CCU_MULT(4, 2),
115 .fixed_post_div = 2,
119 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
126 .enable = BIT(24),
127 .div = _SUNXI_CCU_DIV(0, 2),
129 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
130 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
131 * 6/2 = 3.
137 .hw.init = CLK_HW_INIT("pll-periph0-sata",
138 "pll-periph0",
145 .enable = BIT(31),
146 .lock = BIT(28),
148 .k = _SUNXI_CCU_MULT(4, 2),
149 .fixed_post_div = 2,
153 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
159 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
165 BIT(24), /* frac enable */
166 BIT(25), /* frac select */
169 BIT(31), /* gate */
170 BIT(28), /* lock */
174 .enable = BIT(31),
175 .lock = BIT(28),
177 .k = _SUNXI_CCU_MULT(4, 2),
178 .m = _SUNXI_CCU_DIV(0, 2),
183 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
189 static const char * const pll_sata_out_parents[] = { "pll-sata",
190 "pll-periph0-sata" };
191 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
194 BIT(14), /* gate */
198 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
202 BIT(24), /* frac enable */
203 BIT(25), /* frac select */
206 BIT(31), /* gate */
207 BIT(28), /* lock */
211 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
213 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
222 static const char * const pll_mipi_parents[] = { "pll-video0" };
224 .enable = BIT(31) | BIT(23) | BIT(22),
225 .lock = BIT(28),
227 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
232 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
240 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
244 BIT(24), /* frac enable */
245 BIT(25), /* frac select */
248 BIT(31), /* gate */
249 BIT(28), /* lock */
253 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
256 0, 2, /* M */
257 BIT(31), /* gate */
258 BIT(28), /* lock */
262 "pll-cpu", "pll-cpu" };
264 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
266 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
269 "axi", "pll-periph0" };
271 { .index = 3, .shift = 6, .width = 2 },
274 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
278 .width = 2,
295 { .val = 0, .div = 2 },
296 { .val = 1, .div = 2 },
297 { .val = 2, .div = 4 },
302 0x054, 8, 2, apb1_div_table, 0);
305 "pll-periph0-2x",
306 "pll-periph0-2x" };
309 16, 2, /* P */
310 24, 2, /* mux */
313 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
314 0x060, BIT(1), 0);
315 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
316 0x060, BIT(5), 0);
317 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
318 0x060, BIT(6), 0);
319 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
320 0x060, BIT(8), 0);
321 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
322 0x060, BIT(9), 0);
323 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
324 0x060, BIT(10), 0);
325 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
326 0x060, BIT(11), 0);
327 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
328 0x060, BIT(13), 0);
329 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
330 0x060, BIT(14), 0);
331 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
332 0x060, BIT(17), 0);
333 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
334 0x060, BIT(18), 0);
335 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
336 0x060, BIT(19), 0);
337 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
338 0x060, BIT(20), 0);
339 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
340 0x060, BIT(21), 0);
341 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
342 0x060, BIT(22), 0);
343 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
344 0x060, BIT(23), 0);
345 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
346 0x060, BIT(24), 0);
347 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
348 0x060, BIT(25), 0);
349 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
350 0x060, BIT(26), 0);
351 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
352 0x060, BIT(27), 0);
353 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
354 0x060, BIT(28), 0);
355 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
356 0x060, BIT(29), 0);
357 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
358 0x060, BIT(30), 0);
359 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
360 0x060, BIT(31), 0);
362 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
363 0x064, BIT(0), 0);
364 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
365 0x064, BIT(2), 0);
366 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
367 0x064, BIT(5), 0);
368 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
369 0x064, BIT(8), 0);
370 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
371 0x064, BIT(9), 0);
372 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
373 0x064, BIT(10), 0);
374 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
375 0x064, BIT(11), 0);
376 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
377 0x064, BIT(12), 0);
378 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
379 0x064, BIT(13), 0);
380 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
381 0x064, BIT(14), 0);
382 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
383 0x064, BIT(15), 0);
384 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
385 0x064, BIT(17), 0);
386 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
387 0x064, BIT(20), 0);
388 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
389 0x064, BIT(21), 0);
390 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
391 0x064, BIT(22), 0);
392 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
393 0x064, BIT(23), 0);
394 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
395 0x064, BIT(24), 0);
396 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
397 0x064, BIT(25), 0);
398 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
399 0x064, BIT(26), 0);
400 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
401 0x064, BIT(27), 0);
402 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
403 0x064, BIT(28), 0);
404 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
405 0x064, BIT(29), 0);
406 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
407 0x064, BIT(30), 0);
409 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
410 0x068, BIT(0), 0);
411 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
412 0x068, BIT(1), 0);
413 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
414 0x068, BIT(2), 0);
415 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
416 0x068, BIT(5), 0);
417 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
418 0x068, BIT(6), 0);
419 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
420 0x068, BIT(7), 0);
421 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
422 0x068, BIT(8), 0);
423 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
424 0x068, BIT(10), 0);
425 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
426 0x068, BIT(12), 0);
427 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
428 0x068, BIT(13), 0);
429 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
430 0x068, BIT(14), 0);
432 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
433 0x06c, BIT(0), 0);
434 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
435 0x06c, BIT(1), 0);
436 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
437 0x06c, BIT(2), 0);
438 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
439 0x06c, BIT(3), 0);
444 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
445 0x06c, BIT(4), 0);
446 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
447 0x06c, BIT(5), 0);
448 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
449 0x06c, BIT(6), 0);
450 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
451 0x06c, BIT(7), 0);
452 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
453 0x06c, BIT(15), 0);
454 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
455 0x06c, BIT(16), 0);
456 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
457 0x06c, BIT(17), 0);
458 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
459 0x06c, BIT(18), 0);
460 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
461 0x06c, BIT(19), 0);
462 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
463 0x06c, BIT(20), 0);
464 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
465 0x06c, BIT(21), 0);
466 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
467 0x06c, BIT(22), 0);
468 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
469 0x06c, BIT(23), 0);
471 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
472 0x070, BIT(7), 0);
476 .enable = BIT(31),
477 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
478 .mux = _SUNXI_CCU_MUX(24, 2),
488 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
489 "pll-periph1" };
492 16, 2, /* P */
493 24, 2, /* mux */
494 BIT(31), /* gate */
499 16, 2, /* P */
500 24, 2, /* mux */
501 BIT(31), /* gate */
506 16, 2, /* P */
507 24, 2, /* mux */
508 BIT(31), /* gate */
513 16, 2, /* P */
514 24, 2, /* mux */
515 BIT(31), /* gate */
520 16, 2, /* P */
521 24, 2, /* mux */
522 BIT(31), /* gate */
525 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
528 16, 2, /* P */
530 BIT(31), /* gate */
533 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
534 "pll-periph1-2x" };
537 16, 2, /* P */
538 24, 2, /* mux */
539 BIT(31), /* gate */
544 16, 2, /* P */
545 24, 2, /* mux */
546 BIT(31), /* gate */
551 16, 2, /* P */
552 24, 2, /* mux */
553 BIT(31), /* gate */
558 16, 2, /* P */
559 24, 2, /* mux */
560 BIT(31), /* gate */
565 16, 2, /* P */
566 24, 2, /* mux */
567 BIT(31), /* gate */
570 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
571 "pll-audio-2x", "pll-audio" };
573 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
576 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
579 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
582 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
585 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
588 static const u8 keypad_table[] = { 0, 2 };
590 .enable = BIT(31),
592 .p = _SUNXI_CCU_DIV(16, 2),
593 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
603 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
605 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
613 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
614 0x0cc, BIT(8), 0);
615 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
616 0x0cc, BIT(9), 0);
617 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
618 0x0cc, BIT(10), 0);
619 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
620 0x0cc, BIT(16), 0);
621 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
622 0x0cc, BIT(17), 0);
623 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
624 0x0cc, BIT(18), 0);
626 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
627 "pll-periph1", "osc32k" };
630 16, 2, /* P */
631 24, 2, /* mux */
632 BIT(31), /* gate */
637 16, 2, /* P */
638 24, 2, /* mux */
639 BIT(31), /* gate */
642 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
644 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
646 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
647 0x100, BIT(0), 0);
648 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
649 0x100, BIT(1), 0);
650 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
651 0x100, BIT(2), 0);
652 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
653 0x100, BIT(3), 0);
654 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
655 0x100, BIT(4), 0);
656 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
657 0x100, BIT(5), 0);
658 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
659 0x100, BIT(6), 0);
661 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
663 0x104, 0, 4, 24, 3, BIT(31),
666 0x108, 0, 4, 24, 3, BIT(31), 0);
668 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
669 "pll-video0-2x", "pll-video1-2x",
670 "pll-mipi" };
671 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
672 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
673 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
674 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
675 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
676 0x118, 0, 4, 24, 3, BIT(31),
678 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
679 0x11c, 0, 4, 24, 3, BIT(31),
682 static const char * const deinterlace_parents[] = { "pll-periph0",
683 "pll-periph1" };
686 BIT(31), 0);
688 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
689 "pll-periph1" };
690 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
691 0x130, 0, 5, 8, 3, BIT(15), 0);
693 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
694 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
695 0x134, 16, 4, 24, 3, BIT(31), 0);
697 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
698 0x134, 0, 5, 8, 3, BIT(15), 0);
700 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
701 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
703 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
704 0x140, BIT(31), CLK_SET_RATE_PARENT);
706 0x144, BIT(31), 0);
708 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
710 0x150, 0, 4, 24, 2, BIT(31),
713 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
714 0x154, BIT(31), 0);
723 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
724 "pll-ddr0" };
727 16, 2, /* P */
728 24, 2, /* mux */
729 BIT(31), /* gate */
732 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
733 "pll-periph0" };
734 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
735 0x168, 0, 4, 8, 2, BIT(15), 0);
738 0x180, 0, 4, 24, 3, BIT(31), 0);
740 0x184, 0, 4, 24, 3, BIT(31), 0);
742 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
743 "pll-video0-2x", "pll-video1-2x" };
745 0x188, 0, 4, 24, 3, BIT(31), 0);
747 0x18c, 0, 4, 24, 3, BIT(31), 0);
749 0x190, 0, 4, 24, 3, BIT(31), 0);
751 0x194, 0, 4, 24, 3, BIT(31), 0);
753 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
754 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
762 .enable = BIT(31),
764 .p = _SUNXI_CCU_DIV(20, 2),
767 .width = 2,
781 .enable = BIT(31),
783 .p = _SUNXI_CCU_DIV(20, 2),
786 .width = 2,
960 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
967 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
970 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
972 2, 1, CLK_SET_RATE_PARENT);
973 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
976 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
978 1, 2, CLK_SET_RATE_PARENT);
979 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
981 1, 2, 0);
982 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
984 1, 2, 0);
985 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
987 1, 2, 0);
988 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
990 1, 2, 0);
1165 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1166 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1167 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1169 [RST_DRAM] = { 0x0f4, BIT(31) },
1170 [RST_MBUS] = { 0x0fc, BIT(31) },
1172 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
1173 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1174 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1175 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1176 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1177 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1178 [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
1179 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1180 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1181 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1182 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1183 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1184 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1185 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1186 [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
1187 [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
1188 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1189 [RST_BUS_OTG] = { 0x2c0, BIT(25) },
1190 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
1191 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
1192 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
1193 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
1194 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
1195 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
1197 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1198 [RST_BUS_MP] = { 0x2c4, BIT(2) },
1199 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1200 [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
1201 [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
1202 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1203 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1204 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1205 [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
1206 [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
1207 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
1208 [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
1209 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1210 [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
1211 [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
1212 [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
1213 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1214 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
1215 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
1216 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
1217 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
1218 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
1219 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
1220 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1222 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
1224 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1225 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1226 [RST_BUS_AC97] = { 0x2d0, BIT(2) },
1227 [RST_BUS_IR0] = { 0x2d0, BIT(6) },
1228 [RST_BUS_IR1] = { 0x2d0, BIT(7) },
1229 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1230 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
1231 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1232 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1233 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1235 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1236 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1237 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1238 [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
1239 [RST_BUS_CAN] = { 0x2d8, BIT(4) },
1240 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
1241 [RST_BUS_PS20] = { 0x2d8, BIT(6) },
1242 [RST_BUS_PS21] = { 0x2d8, BIT(7) },
1243 [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
1244 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1245 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1246 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1247 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1248 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
1249 [RST_BUS_UART5] = { 0x2d8, BIT(21) },
1250 [RST_BUS_UART6] = { 0x2d8, BIT(22) },
1251 [RST_BUS_UART7] = { 0x2d8, BIT(23) },
1267 .enable = BIT(31),
1268 .lock = BIT(28),
1279 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1317 reg = devm_ioremap_resource(&pdev->dev, res); in sun8i_r40_ccu_probe()
1321 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_r40_ccu_probe()
1326 /* Force PLL-MIPI to MIPI mode */ in sun8i_r40_ccu_probe()
1328 val &= ~BIT(16); in sun8i_r40_ccu_probe()
1341 writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8), in sun8i_r40_ccu_probe()
1344 regmap = devm_regmap_init_mmio(&pdev->dev, reg, in sun8i_r40_ccu_probe()
1349 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); in sun8i_r40_ccu_probe()
1364 { .compatible = "allwinner,sun8i-r40-ccu" },
1371 .name = "sun8i-r40-ccu",