Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
54 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
64 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
66 #define GMAC_RXQCTRL_TACPQE BIT(21)
72 #define GMAC_PACKET_FILTER_PR BIT(0)
73 #define GMAC_PACKET_FILTER_HMC BIT(2)
74 #define GMAC_PACKET_FILTER_PM BIT(4)
75 #define GMAC_PACKET_FILTER_PCF BIT(7)
76 #define GMAC_PACKET_FILTER_HPF BIT(10)
77 #define GMAC_PACKET_FILTER_VTFE BIT(16)
78 #define GMAC_PACKET_FILTER_IPFE BIT(20)
79 #define GMAC_PACKET_FILTER_RA BIT(31)
84 #define GMAC_VLAN_EDVLP BIT(26)
85 #define GMAC_VLAN_VTHM BIT(25)
86 #define GMAC_VLAN_DOVLTC BIT(20)
87 #define GMAC_VLAN_ESVL BIT(18)
88 #define GMAC_VLAN_ETV BIT(16)
90 #define GMAC_VLAN_VLTI BIT(20)
91 #define GMAC_VLAN_CSVL BIT(19)
98 #define GMAC_VLAN_TAG_ETV BIT(16)
101 #define GMAC_VLAN_TAG_CTRL_OB BIT(0)
102 #define GMAC_VLAN_TAG_CTRL_CT BIT(1)
103 #define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)
104 #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2
107 #define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24)
116 #define GMAC_VLAN_TAG_DATA_VEN BIT(16)
117 #define GMAC_VLAN_TAG_DATA_ETV BIT(17)
120 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
121 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
122 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
125 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
136 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
140 #define GMAC_INT_RGSMIIS BIT(0)
141 #define GMAC_INT_PCS_LINK BIT(1)
142 #define GMAC_INT_PCS_ANE BIT(2)
143 #define GMAC_INT_PCS_PHYIS BIT(3)
144 #define GMAC_INT_PMT_EN BIT(4)
145 #define GMAC_INT_LPI_EN BIT(5)
181 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
182 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
183 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
184 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
185 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
186 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
187 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
188 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
195 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
197 #define GMAC_DEBUG_TPESTS BIT(16)
198 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
200 #define GMAC_DEBUG_RPESTS BIT(0)
203 #define GMAC_CONFIG_ARPEN BIT(31)
206 #define GMAC_CONFIG_IPC BIT(27)
209 #define GMAC_CONFIG_2K BIT(22)
210 #define GMAC_CONFIG_ACS BIT(20)
211 #define GMAC_CONFIG_BE BIT(18)
212 #define GMAC_CONFIG_JD BIT(17)
213 #define GMAC_CONFIG_JE BIT(16)
214 #define GMAC_CONFIG_PS BIT(15)
215 #define GMAC_CONFIG_FES BIT(14)
217 #define GMAC_CONFIG_DM BIT(13)
218 #define GMAC_CONFIG_LM BIT(12)
219 #define GMAC_CONFIG_DCRS BIT(9)
220 #define GMAC_CONFIG_TE BIT(1)
221 #define GMAC_CONFIG_RE BIT(0)
226 #define GMAC_CONFIG_EIPG_EN BIT(24)
232 #define GMAC_HW_FEAT_SAVLANINS BIT(27)
233 #define GMAC_HW_FEAT_ADDMAC BIT(18)
234 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
235 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
236 #define GMAC_HW_FEAT_EEESEL BIT(13)
237 #define GMAC_HW_FEAT_TSSEL BIT(12)
238 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
239 #define GMAC_HW_FEAT_MMCSEL BIT(8)
240 #define GMAC_HW_FEAT_MGKSEL BIT(7)
241 #define GMAC_HW_FEAT_RWKSEL BIT(6)
242 #define GMAC_HW_FEAT_SMASEL BIT(5)
243 #define GMAC_HW_FEAT_VLHASH BIT(4)
244 #define GMAC_HW_FEAT_PCSSEL BIT(3)
245 #define GMAC_HW_FEAT_HDSEL BIT(2)
246 #define GMAC_HW_FEAT_GMIISEL BIT(1)
247 #define GMAC_HW_FEAT_MIISEL BIT(0)
252 #define GMAC_HW_FEAT_AVSEL BIT(20)
253 #define GMAC_HW_TSOEN BIT(18)
254 #define GMAC_HW_FEAT_SPHEN BIT(17)
268 #define GMAC_HW_FEAT_TBSSEL BIT(27)
269 #define GMAC_HW_FEAT_FPESEL BIT(26)
272 #define GMAC_HW_FEAT_ESTSEL BIT(16)
275 #define GMAC_HW_FEAT_FRPSEL BIT(10)
276 #define GMAC_HW_FEAT_DVLAN BIT(5)
277 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
282 #define GMAC_HI_REG_AE BIT(31)
285 #define GMAC_L4DPIM0 BIT(21)
286 #define GMAC_L4DPM0 BIT(20)
287 #define GMAC_L4SPIM0 BIT(19)
288 #define GMAC_L4SPM0 BIT(18)
289 #define GMAC_L4PEN0 BIT(16)
290 #define GMAC_L3DAIM0 BIT(5)
291 #define GMAC_L3DAM0 BIT(4)
292 #define GMAC_L3SAIM0 BIT(3)
293 #define GMAC_L3SAM0 BIT(2)
294 #define GMAC_L3PEN0 BIT(0)
301 #define MTL_FRPE BIT(15)
307 #define MTL_OPERATION_RAA BIT(2)
308 #define MTL_OPERATION_RAA_SP (0x0 << 2)
309 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
312 #define MTL_INT_QX(x) BIT(x)
318 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
332 #define MTL_OP_MODE_RSF BIT(5)
333 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
334 #define MTL_OP_MODE_TXQEN_AV BIT(2)
335 #define MTL_OP_MODE_TXQEN BIT(3)
336 #define MTL_OP_MODE_TSF BIT(1)
346 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
362 #define MTL_OP_MODE_EHFC BIT(7)
369 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
378 #define MTL_ETS_CTRL_CC BIT(3)
379 #define MTL_ETS_CTRL_AVALG BIT(2)
413 #define MTL_DEBUG_TXSTSFSTS BIT(5)
414 #define MTL_DEBUG_TXFSTS BIT(4)
415 #define MTL_DEBUG_TWCSTS BIT(3)
418 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
422 #define MTL_DEBUG_TRCSTS_TXW 2
424 #define MTL_DEBUG_TXPAUSED BIT(0)
431 #define MTL_DEBUG_RXFSTS_AT 2
433 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
437 #define MTL_DEBUG_RRCSTS_RSTAT 2
439 #define MTL_DEBUG_RWCSTS BIT(0)
442 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
443 #define MTL_RX_OVERFLOW_INT BIT(16)
454 #define MTL_DEBUG_TXSTSFSTS BIT(5)
455 #define MTL_DEBUG_TXFSTS BIT(4)
456 #define MTL_DEBUG_TWCSTS BIT(3)
459 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
463 #define MTL_DEBUG_TRCSTS_TXW 2
465 #define MTL_DEBUG_TXPAUSED BIT(0)
472 #define MTL_DEBUG_RXFSTS_AT 2
474 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
478 #define MTL_DEBUG_RRCSTS_RSTAT 2
480 #define MTL_DEBUG_RWCSTS BIT(0)
483 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
484 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
485 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
486 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
489 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
490 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
491 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)