Lines Matching +full:2 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
28 .enable = BIT(31),
29 .lock = BIT(28),
32 .k = _SUNXI_CCU_MULT(4, 2),
33 .m = _SUNXI_CCU_DIV(0, 2),
34 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
38 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 * the base (2x, 4x and 8x), and one variable divider (the one true
49 * With sigma-delta modulation for fractional-N on the audio PLL,
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 pll_audio_sdm_table, BIT(24),
68 0x284, BIT(31),
69 BIT(31), /* gate */
70 BIT(28), /* lock */
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
81 BIT(31), /* gate */
82 BIT(28), /* lock */
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
100 4, 2, /* K */
101 0, 2, /* M */
102 BIT(31), /* gate */
103 BIT(28), /* lock */
106 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
109 4, 2, /* K */
110 BIT(31), /* gate */
111 BIT(28), /* lock */
112 2, /* post-div */
115 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
119 BIT(24), /* frac enable */
120 BIT(25), /* frac select */
123 BIT(31), /* gate */
124 BIT(28), /* lock */
128 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
130 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
135 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
136 "pll-video", 0x040,
138 4, 2, /* K */
140 BIT(31) | BIT(23) | BIT(22), /* gate */
141 BIT(28), /* lock */
144 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
148 BIT(24), /* frac enable */
149 BIT(25), /* frac select */
152 BIT(31), /* gate */
153 BIT(28), /* lock */
156 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
160 BIT(24), /* frac enable */
161 BIT(25), /* frac select */
164 BIT(31), /* gate */
165 BIT(28), /* lock */
169 "pll-cpux" , "pll-cpux" };
171 0x050, 16, 2, CLK_IS_CRITICAL);
173 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
176 "axi" , "pll-periph" };
178 { .index = 3, .shift = 6, .width = 2 },
181 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
185 .width = 2,
202 { .val = 0, .div = 2 },
203 { .val = 1, .div = 2 },
204 { .val = 2, .div = 4 },
209 0x054, 8, 2, apb1_div_table, 0);
212 "pll-periph" , "pll-periph" };
215 16, 2, /* P */
216 24, 2, /* mux */
219 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
220 0x060, BIT(1), 0);
221 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
222 0x060, BIT(6), 0);
223 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
224 0x060, BIT(8), 0);
225 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
226 0x060, BIT(9), 0);
227 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
228 0x060, BIT(10), 0);
229 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
230 0x060, BIT(13), 0);
231 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
232 0x060, BIT(14), 0);
233 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
234 0x060, BIT(19), 0);
235 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
236 0x060, BIT(20), 0);
237 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
238 0x060, BIT(21), 0);
239 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
240 0x060, BIT(24), 0);
241 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
242 0x060, BIT(26), 0);
243 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
244 0x060, BIT(29), 0);
246 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
247 0x064, BIT(0), 0);
248 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
249 0x064, BIT(4), 0);
250 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
251 0x064, BIT(8), 0);
252 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
253 0x064, BIT(12), 0);
254 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
255 0x064, BIT(14), 0);
256 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
257 0x064, BIT(20), 0);
258 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
259 0x064, BIT(21), 0);
260 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
261 0x064, BIT(22), 0);
262 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
263 0x064, BIT(25), 0);
265 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
266 0x068, BIT(0), 0);
267 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
268 0x068, BIT(5), 0);
269 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
270 0x068, BIT(12), 0);
271 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
272 0x068, BIT(13), 0);
274 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
275 0x06c, BIT(0), 0);
276 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
277 0x06c, BIT(1), 0);
278 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
279 0x06c, BIT(2), 0);
280 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
281 0x06c, BIT(16), 0);
282 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
283 0x06c, BIT(17), 0);
284 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
285 0x06c, BIT(18), 0);
286 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
287 0x06c, BIT(19), 0);
288 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
289 0x06c, BIT(20), 0);
291 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
294 16, 2, /* P */
295 24, 2, /* mux */
296 BIT(31), /* gate */
301 16, 2, /* P */
302 24, 2, /* mux */
303 BIT(31), /* gate */
313 16, 2, /* P */
314 24, 2, /* mux */
315 BIT(31), /* gate */
325 16, 2, /* P */
326 24, 2, /* mux */
327 BIT(31), /* gate */
337 16, 2, /* P */
338 24, 2, /* mux */
339 BIT(31), /* gate */
344 16, 2, /* P */
345 24, 2, /* mux */
346 BIT(31), /* gate */
349 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
350 "pll-audio-2x", "pll-audio" };
352 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
355 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
358 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
359 0x0cc, BIT(8), 0);
360 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
361 0x0cc, BIT(9), 0);
362 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
363 0x0cc, BIT(10), 0);
364 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
365 0x0cc, BIT(11), 0);
366 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
367 0x0cc, BIT(16), 0);
369 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
370 0x100, BIT(0), 0);
371 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
372 0x100, BIT(1), 0);
373 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
374 0x100, BIT(16), 0);
375 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
376 0x100, BIT(24), 0);
377 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
378 0x100, BIT(26), 0);
380 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
381 "pll-gpu", "pll-de" };
382 static const u8 de_table[] = { 0, 2, 3, 5 };
383 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
385 0x104, 0, 4, 24, 3, BIT(31), 0);
387 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
389 0x10c, 0, 4, 24, 3, BIT(31), 0);
391 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
392 "pll-mipi" };
393 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
394 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
396 0x118, 24, 3, BIT(31),
399 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
400 static const u8 lcd_ch1_table[] = { 0, 2 };
401 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
403 0x12c, 0, 4, 24, 2, BIT(31), 0);
405 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
406 "pll-mipi", "pll-ve" };
408 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
410 0x134, 16, 4, 24, 3, BIT(31), 0);
412 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
417 0x134, 0, 5, 8, 3, BIT(15), 0);
419 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
420 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
422 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
423 0x140, BIT(31), CLK_SET_RATE_PARENT);
425 0x144, BIT(31), 0);
427 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
428 "pll-ddr" };
430 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
432 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
433 static const u8 dsi_sclk_table[] = { 0, 2 };
434 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
436 0x168, 16, 4, 24, 2, BIT(31), 0);
438 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
439 static const u8 dsi_dphy_table[] = { 0, 2 };
440 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
442 0x168, 0, 4, 8, 2, BIT(15), 0);
446 0x180, 0, 4, 24, 3, BIT(31), 0);
448 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
449 0x1a0, 0, 3, BIT(31), 0);
451 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
453 0x1b0, 0, 3, 24, 2, BIT(31), 0);
551 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
554 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
556 2, 1, CLK_SET_RATE_PARENT);
557 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
560 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
562 1, 2, CLK_SET_RATE_PARENT);
563 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
565 1, 2, 0);
566 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
568 1, 2, 0);
671 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
672 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
673 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
675 [RST_MBUS] = { 0x0fc, BIT(31) },
677 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
678 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
679 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
680 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
681 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
682 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
683 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
684 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
685 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
686 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
687 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
688 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
689 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
691 [RST_BUS_VE] = { 0x2c4, BIT(0) },
692 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
693 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
694 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
695 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
696 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
697 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
698 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
699 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
701 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
703 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
704 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
705 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
707 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
708 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
709 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
710 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
711 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
712 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
713 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
714 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
738 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a23_ccu_setup()
743 /* Force PLL-MIPI to MIPI mode */ in sun8i_a23_ccu_setup()
745 val &= ~BIT(16); in sun8i_a23_ccu_setup()
750 CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",