Lines Matching +full:2 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
29 #include "ccu-sun6i-a31.h"
31 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
34 4, 2, /* K */
35 0, 2, /* M */
36 BIT(31), /* gate */
37 BIT(28), /* lock */
42 * the base (2x, 4x and 8x), and one variable divider (the one true
45 * With sigma-delta modulation for fractional-N on the audio PLL,
59 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 pll_audio_sdm_table, BIT(24),
64 0x284, BIT(31),
65 BIT(31), /* gate */
66 BIT(28), /* lock */
69 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
73 BIT(24), /* frac enable */
74 BIT(25), /* frac select */
77 BIT(31), /* gate */
78 BIT(28), /* lock */
81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
85 BIT(24), /* frac enable */
86 BIT(25), /* frac select */
89 BIT(31), /* gate */
90 BIT(28), /* lock */
93 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
96 4, 2, /* K */
97 0, 2, /* M */
98 BIT(31), /* gate */
99 BIT(28), /* lock */
102 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
105 4, 2, /* K */
106 BIT(31), /* gate */
107 BIT(28), /* lock */
108 2, /* post-div */
111 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
115 BIT(24), /* frac enable */
116 BIT(25), /* frac select */
119 BIT(31), /* gate */
120 BIT(28), /* lock */
123 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
127 BIT(24), /* frac enable */
128 BIT(25), /* frac select */
131 BIT(31), /* gate */
132 BIT(28), /* lock */
136 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
138 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
144 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
145 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
148 4, 2, /* K */
151 BIT(31) | BIT(23) | BIT(22), /* gate */
152 BIT(28), /* lock */
159 BIT(24), /* frac enable */
160 BIT(25), /* frac select */
163 BIT(31), /* gate */
164 BIT(28), /* lock */
171 BIT(24), /* frac enable */
172 BIT(25), /* frac select */
175 BIT(31), /* gate */
176 BIT(28), /* lock */
180 "pll-cpu", "pll-cpu" };
182 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
186 { .val = 1, .div = 2 },
187 { .val = 2, .div = 3 },
202 "axi", "pll-periph" };
204 { .index = 3, .shift = 6, .width = 2 },
208 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
212 .width = 2,
229 { .val = 0, .div = 2 },
230 { .val = 1, .div = 2 },
231 { .val = 2, .div = 4 },
237 0x054, 8, 2, apb1_div_table, 0);
240 "pll-periph", "pll-periph" };
243 16, 2, /* P */
244 24, 2, /* mux */
247 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
248 0x060, BIT(1), 0);
249 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
250 0x060, BIT(5), 0);
251 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
252 0x060, BIT(6), 0);
253 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
254 0x060, BIT(8), 0);
255 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
256 0x060, BIT(9), 0);
257 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
258 0x060, BIT(10), 0);
259 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
260 0x060, BIT(11), 0);
261 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
262 0x060, BIT(12), 0);
263 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
264 0x060, BIT(13), 0);
265 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
266 0x060, BIT(14), 0);
267 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
268 0x060, BIT(17), 0);
269 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
270 0x060, BIT(18), 0);
271 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
272 0x060, BIT(19), 0);
273 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
274 0x060, BIT(20), 0);
275 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
276 0x060, BIT(21), 0);
277 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
278 0x060, BIT(22), 0);
279 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
280 0x060, BIT(23), 0);
281 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
282 0x060, BIT(24), 0);
283 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
284 0x060, BIT(26), 0);
285 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
286 0x060, BIT(27), 0);
287 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
288 0x060, BIT(29), 0);
289 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
290 0x060, BIT(30), 0);
291 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
292 0x060, BIT(31), 0);
294 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
295 0x064, BIT(0), 0);
296 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
297 0x064, BIT(4), 0);
298 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
299 0x064, BIT(5), 0);
300 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
301 0x064, BIT(8), 0);
302 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
303 0x064, BIT(11), 0);
304 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
305 0x064, BIT(12), 0);
306 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
307 0x064, BIT(13), 0);
308 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
309 0x064, BIT(14), 0);
310 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
311 0x064, BIT(15), 0);
312 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
313 0x064, BIT(18), 0);
314 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
315 0x064, BIT(20), 0);
316 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
317 0x064, BIT(23), 0);
318 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
319 0x064, BIT(24), 0);
320 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
321 0x064, BIT(25), 0);
322 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
323 0x064, BIT(26), 0);
325 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
326 0x068, BIT(0), 0);
327 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
328 0x068, BIT(1), 0);
329 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
330 0x068, BIT(4), 0);
331 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
332 0x068, BIT(5), 0);
333 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
334 0x068, BIT(12), 0);
335 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
336 0x068, BIT(13), 0);
338 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
339 0x06c, BIT(0), 0);
340 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
341 0x06c, BIT(1), 0);
342 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
343 0x06c, BIT(2), 0);
344 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
345 0x06c, BIT(3), 0);
346 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
347 0x06c, BIT(16), 0);
348 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
349 0x06c, BIT(17), 0);
350 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
351 0x06c, BIT(18), 0);
352 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
353 0x06c, BIT(19), 0);
354 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
355 0x06c, BIT(20), 0);
356 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
357 0x06c, BIT(21), 0);
359 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
363 16, 2, /* P */
364 24, 2, /* mux */
365 BIT(31), /* gate */
371 16, 2, /* P */
372 24, 2, /* mux */
373 BIT(31), /* gate */
379 16, 2, /* P */
380 24, 2, /* mux */
381 BIT(31), /* gate */
392 16, 2, /* P */
393 24, 2, /* mux */
394 BIT(31), /* gate */
405 16, 2, /* P */
406 24, 2, /* mux */
407 BIT(31), /* gate */
418 16, 2, /* P */
419 24, 2, /* mux */
420 BIT(31), /* gate */
430 16, 2, /* P */
431 24, 2, /* mux */
432 BIT(31), /* gate */
437 16, 2, /* P */
438 24, 2, /* mux */
439 BIT(31), /* gate */
444 16, 2, /* P */
445 24, 2, /* mux */
446 BIT(31), /* gate */
451 16, 2, /* P */
452 24, 2, /* mux */
453 BIT(31), /* gate */
457 16, 2, /* P */
458 24, 2, /* mux */
459 BIT(31), /* gate */
464 16, 2, /* P */
465 24, 2, /* mux */
466 BIT(31), /* gate */
469 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
470 "pll-audio-2x", "pll-audio" };
472 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
474 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
477 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
479 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
480 0x0cc, BIT(8), 0);
481 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
482 0x0cc, BIT(9), 0);
483 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
484 0x0cc, BIT(10), 0);
485 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
486 0x0cc, BIT(16), 0);
487 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
488 0x0cc, BIT(17), 0);
489 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
490 0x0cc, BIT(18), 0);
494 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
497 16, 2, /* P */
498 24, 2, /* mux */
499 BIT(31), /* gate */
507 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
508 0x100, BIT(0), 0);
509 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
510 0x100, BIT(1), 0);
511 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
512 0x100, BIT(3), 0);
513 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
514 0x100, BIT(16), 0);
515 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
516 0x100, BIT(17), 0);
517 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
518 0x100, BIT(18), 0);
519 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
520 0x100, BIT(19), 0);
521 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
522 0x100, BIT(24), 0);
523 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
524 0x100, BIT(25), 0);
525 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
526 0x100, BIT(26), 0);
527 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
528 0x100, BIT(27), 0);
529 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
530 0x100, BIT(28), 0);
532 static const char * const de_parents[] = { "pll-video0", "pll-video1",
533 "pll-periph-2x", "pll-gpu",
536 0x104, 0, 4, 24, 3, BIT(31), 0);
538 0x108, 0, 4, 24, 3, BIT(31), 0);
540 0x10c, 0, 4, 24, 3, BIT(31), 0);
542 0x110, 0, 4, 24, 3, BIT(31), 0);
544 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
547 0x114, 0, 4, 24, 3, BIT(31), 0);
549 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
550 "pll-video0-2x",
551 "pll-video1-2x", "pll-mipi" };
552 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
553 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
554 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
555 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
557 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
558 "pll-video0-2x",
559 "pll-video1-2x" };
560 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
561 0x12c, 0, 4, 24, 3, BIT(31),
563 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
564 0x130, 0, 4, 24, 3, BIT(31),
567 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
568 "pll9", "pll10", "pll-mipi",
569 "pll-ve" };
570 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
571 0x134, 16, 4, 24, 3, BIT(31), 0);
573 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
577 .enable = BIT(15),
582 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
590 .enable = BIT(15),
595 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
602 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
603 0x13c, 16, 3, BIT(31), 0);
605 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
606 0x140, BIT(31), CLK_SET_RATE_PARENT);
608 0x144, BIT(31), 0);
609 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
610 0x148, BIT(31), CLK_SET_RATE_PARENT);
613 0x150, 0, 4, 24, 2, BIT(31),
616 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
618 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
620 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
621 "pll-ddr" };
624 16, 2, /* P */
625 24, 2, /* mux */
626 BIT(31), /* gate */
631 16, 2, /* P */
632 24, 2, /* mux */
633 BIT(31), /* gate */
636 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
637 0x168, 16, 3, 24, 2, BIT(31),
639 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
640 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
641 BIT(15), CLK_SET_RATE_PARENT);
642 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
643 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
644 BIT(15), 0);
646 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
647 0x180, 0, 3, 24, 2, BIT(31), 0);
648 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
649 0x184, 0, 3, 24, 2, BIT(31), 0);
650 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
651 0x188, 0, 3, 24, 2, BIT(31), 0);
652 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
653 0x18c, 0, 3, 24, 2, BIT(31), 0);
655 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
656 "pll-video0", "pll-video1",
663 .enable = BIT(31),
674 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
682 .enable = BIT(31),
693 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
701 .enable = BIT(31),
712 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
721 24, 2, /* mux */
722 BIT(31), /* gate */
728 24, 2, /* mux */
729 BIT(31), /* gate */
734 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
743 .enable = BIT(31),
745 .p = _SUNXI_CCU_DIV(20, 2),
756 .hw.init = CLK_HW_INIT_PARENTS("out-a",
764 .enable = BIT(31),
766 .p = _SUNXI_CCU_DIV(20, 2),
777 .hw.init = CLK_HW_INIT_PARENTS("out-b",
785 .enable = BIT(31),
787 .p = _SUNXI_CCU_DIV(20, 2),
798 .hw.init = CLK_HW_INIT_PARENTS("out-c",
963 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
966 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
968 2, 1, CLK_SET_RATE_PARENT);
969 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
972 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
974 1, 2, CLK_SET_RATE_PARENT);
975 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
977 1, 2, 0);
978 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
980 1, 2, CLK_SET_RATE_PARENT);
981 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
983 1, 2, CLK_SET_RATE_PARENT);
1149 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1150 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1151 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1153 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1154 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1155 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1156 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1157 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1158 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1159 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1160 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1161 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1162 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1163 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1164 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1165 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1166 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1167 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1168 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1169 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1170 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1171 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1172 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1173 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1174 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1175 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1177 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1178 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1179 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1180 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1181 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1182 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1183 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1184 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1185 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1186 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1187 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1188 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1189 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1190 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1191 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1192 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1194 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1195 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1196 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1197 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1198 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1200 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1201 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1202 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1203 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1204 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1205 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1206 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1207 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1208 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1209 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1240 /* Force the PLL-Audio-1x divider to 1 */ in sun6i_a31_ccu_setup()
1245 /* Force PLL-MIPI to MIPI mode */ in sun6i_a31_ccu_setup()
1247 val &= BIT(16); in sun6i_a31_ccu_setup()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_setup()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_setup()
1265 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",