Lines Matching +full:2 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
44 * the base (2x, 4x and 8x), and one variable divider (the one true
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 pll_audio_sdm_table, BIT(24),
66 0x284, BIT(31),
67 BIT(31), /* gate */
68 BIT(28), /* lock */
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
81 BIT(31), /* gate */
82 BIT(28), /* lock */
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
100 4, 2, /* K */
101 0, 2, /* M */
102 BIT(31), /* gate */
103 BIT(28), /* lock */
107 .enable = BIT(31),
108 .lock = BIT(28),
110 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
111 .fixed_post_div = 2,
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
121 .enable = BIT(31),
122 .lock = BIT(28),
124 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
125 .fixed_post_div = 2,
129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
140 BIT(24), /* frac enable */
141 BIT(25), /* frac select */
144 BIT(31), /* gate */
145 BIT(28), /* lock */
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
152 BIT(24), /* frac enable */
153 BIT(25), /* frac select */
156 BIT(31), /* gate */
157 BIT(28), /* lock */
170 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
174 .enable = BIT(31) | BIT(23) | BIT(22),
175 .lock = BIT(28),
177 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
181 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
186 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
190 BIT(24), /* frac enable */
191 BIT(25), /* frac select */
194 BIT(31), /* gate */
195 BIT(28), /* lock */
198 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
202 BIT(24), /* frac enable */
203 BIT(25), /* frac select */
206 BIT(31), /* gate */
207 BIT(28), /* lock */
210 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
213 0, 2, /* M */
214 BIT(31), /* gate */
215 BIT(28), /* lock */
219 "pll-cpux", "pll-cpux" };
221 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
223 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
226 "axi", "pll-periph0" };
228 { .index = 3, .shift = 6, .width = 2 },
231 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
235 .width = 2,
252 { .val = 0, .div = 2 },
253 { .val = 1, .div = 2 },
254 { .val = 2, .div = 4 },
259 0x054, 8, 2, apb1_div_table, 0);
262 "pll-periph0-2x",
263 "pll-periph0-2x" };
266 16, 2, /* P */
267 24, 2, /* mux */
270 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
272 { .index = 1, .div = 2 },
292 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
293 0x060, BIT(1), 0);
294 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
295 0x060, BIT(5), 0);
296 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
297 0x060, BIT(6), 0);
298 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
299 0x060, BIT(8), 0);
300 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
301 0x060, BIT(9), 0);
302 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
303 0x060, BIT(10), 0);
304 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
305 0x060, BIT(13), 0);
306 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
307 0x060, BIT(14), 0);
308 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
309 0x060, BIT(17), 0);
310 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
311 0x060, BIT(18), 0);
312 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
313 0x060, BIT(19), 0);
314 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
315 0x060, BIT(20), 0);
316 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
317 0x060, BIT(21), 0);
318 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
319 0x060, BIT(23), 0);
320 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
321 0x060, BIT(24), 0);
322 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
323 0x060, BIT(25), 0);
324 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
325 0x060, BIT(28), 0);
326 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
327 0x060, BIT(29), 0);
329 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
330 0x064, BIT(0), 0);
331 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
332 0x064, BIT(3), 0);
333 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
334 0x064, BIT(4), 0);
335 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
336 0x064, BIT(5), 0);
337 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
338 0x064, BIT(8), 0);
339 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
340 0x064, BIT(11), 0);
341 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
342 0x064, BIT(12), 0);
343 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
344 0x064, BIT(20), 0);
345 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
346 0x064, BIT(21), 0);
347 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
348 0x064, BIT(22), 0);
350 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
351 0x068, BIT(0), 0);
352 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
353 0x068, BIT(1), 0);
354 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
355 0x068, BIT(5), 0);
356 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
357 0x068, BIT(8), 0);
358 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
359 0x068, BIT(12), 0);
360 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
361 0x068, BIT(13), 0);
362 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
363 0x068, BIT(14), 0);
365 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
366 0x06c, BIT(0), 0);
367 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
368 0x06c, BIT(1), 0);
369 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
370 0x06c, BIT(2), 0);
371 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
372 0x06c, BIT(5), 0);
373 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
374 0x06c, BIT(16), 0);
375 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
376 0x06c, BIT(17), 0);
377 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
378 0x06c, BIT(18), 0);
379 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
380 0x06c, BIT(19), 0);
381 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
382 0x06c, BIT(20), 0);
384 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
385 0x070, BIT(7), 0);
389 { .val = 1, .div = 2 },
390 { .val = 2, .div = 4 },
395 .enable = BIT(31),
396 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
397 .mux = _SUNXI_CCU_MUX(24, 2),
407 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
408 "pll-periph1" };
411 16, 2, /* P */
412 24, 2, /* mux */
413 BIT(31), /* gate */
418 * the mode switch. This means they have a 2x post divider between the clock
424 * The alternative would be to add the 2x multiplier when setting the MMC
427 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
428 "pll-periph1-2x" };
432 16, 2, /* P */
433 24, 2, /* mux */
434 BIT(31), /* gate */
435 2, /* post-div */
441 16, 2, /* P */
442 24, 2, /* mux */
443 BIT(31), /* gate */
444 2, /* post-div */
450 16, 2, /* P */
451 24, 2, /* mux */
452 BIT(31), /* gate */
453 2, /* post-div */
456 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
459 16, 2, /* P */
461 BIT(31), /* gate */
466 16, 2, /* P */
467 24, 2, /* mux */
468 BIT(31), /* gate */
473 16, 2, /* P */
474 24, 2, /* mux */
475 BIT(31), /* gate */
480 16, 2, /* P */
481 24, 2, /* mux */
482 BIT(31), /* gate */
485 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
486 "pll-audio-2x", "pll-audio" };
488 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
491 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
494 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
496 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
497 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
499 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
500 0x0cc, BIT(8), 0);
501 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
502 0x0cc, BIT(9), 0);
503 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
504 0x0cc, BIT(10), 0);
505 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
506 0x0cc, BIT(11), 0);
507 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
508 0x0cc, BIT(16), 0);
509 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
510 0x0cc, BIT(17), 0);
512 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
514 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
516 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
517 0x100, BIT(0), 0);
518 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
519 0x100, BIT(1), 0);
520 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
521 0x100, BIT(2), 0);
522 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
523 0x100, BIT(3), 0);
525 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
527 0x104, 0, 4, 24, 3, BIT(31),
530 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
531 static const u8 tcon0_table[] = { 0, 2, };
533 tcon0_table, 0x118, 24, 3, BIT(31),
536 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
537 static const u8 tcon1_table[] = { 0, 2, };
539 .enable = BIT(31),
541 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
551 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
553 0x124, 0, 4, 24, 3, BIT(31), 0);
555 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
556 0x130, BIT(31), 0);
558 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
559 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
560 0x134, 16, 4, 24, 3, BIT(31), 0);
562 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
563 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
564 0x134, 0, 5, 8, 3, BIT(15), 0);
566 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
567 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
569 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
570 0x140, BIT(31), CLK_SET_RATE_PARENT);
572 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
573 0x140, BIT(30), CLK_SET_RATE_PARENT);
576 0x144, BIT(31), 0);
578 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
580 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
582 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
583 0x154, BIT(31), 0);
585 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
586 "pll-ddr0", "pll-ddr1" };
588 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
590 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
591 static const u8 dsi_dphy_table[] = { 0, 2, };
592 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
594 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
596 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
597 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
600 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
607 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
610 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
612 2, 1, CLK_SET_RATE_PARENT);
613 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
616 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
618 1, 2, CLK_SET_RATE_PARENT);
619 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
621 1, 2, 0);
622 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
624 1, 2, 0);
625 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
627 1, 2, CLK_SET_RATE_PARENT);
855 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
856 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
857 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
859 [RST_DRAM] = { 0x0f4, BIT(31) },
860 [RST_MBUS] = { 0x0fc, BIT(31) },
862 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
863 [RST_BUS_CE] = { 0x2c0, BIT(5) },
864 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
865 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
866 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
867 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
868 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
869 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
870 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
871 [RST_BUS_TS] = { 0x2c0, BIT(18) },
872 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
873 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
874 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
875 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
876 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
877 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
878 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
879 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
881 [RST_BUS_VE] = { 0x2c4, BIT(0) },
882 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
883 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
884 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
885 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
886 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
887 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
888 [RST_BUS_DE] = { 0x2c4, BIT(12) },
889 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
890 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
891 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
892 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
894 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
896 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
897 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
898 [RST_BUS_THS] = { 0x2d0, BIT(8) },
899 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
900 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
901 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
903 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
904 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
905 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
906 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
907 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
908 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
909 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
910 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
911 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
927 .enable = BIT(31),
928 .lock = BIT(28),
946 reg = devm_ioremap_resource(&pdev->dev, res); in sun50i_a64_ccu_probe()
950 /* Force the PLL-Audio-1x divider to 1 */ in sun50i_a64_ccu_probe()
957 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); in sun50i_a64_ccu_probe()
972 { .compatible = "allwinner,sun50i-a64-ccu" },
979 .name = "sun50i-a64-ccu",