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/Linux-v5.10/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Linux-v5.10/arch/mips/include/asm/
Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-frontend.yaml70 const: 0
72 port@0:
107 reg = <0x01e00000 0x20000>;
117 #size-cells = <0>;
121 #size-cells = <0>;
124 fe0_out_be0: endpoint@0 {
125 reg = <0>;
/Linux-v5.10/arch/arm/mach-davinci/
Dusb-da8xx.c24 #define DA8XX_USB0_BASE 0x01e00000
25 #define DA8XX_USB1_BASE 0x01e25000
103 [0] = {
Ddavinci.h38 #define DAVINCI_PLL1_BASE 0x01c40800
39 #define DAVINCI_PLL2_BASE 0x01c40c00
40 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
42 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
43 #define SYSMOD_VDAC_CONFIG 0x2c
44 #define SYSMOD_VIDCLKCTL 0x38
45 #define SYSMOD_VPSS_CLKCTL 0x44
46 #define SYSMOD_VDD3P3VPWDN 0x48
47 #define SYSMOD_VSCLKDIS 0x6c
48 #define SYSMOD_PUPDCTL1 0x7c
[all …]
Ddevices.c24 #define DAVINCI_I2C_BASE 0x01C21000
25 #define DAVINCI_ATA_BASE 0x01C66000
26 #define DAVINCI_MMCSD0_BASE 0x01E10000
27 #define DM355_MMCSD0_BASE 0x01E11000
28 #define DM355_MMCSD1_BASE 0x01E00000
29 #define DM365_MMCSD0_BASE 0x01D11000
30 #define DM365_MMCSD1_BASE 0x01D00000
37 0x800); in davinci_map_sysmod()
49 .end = DAVINCI_I2C_BASE + 0x40,
77 .end = DAVINCI_ATA_BASE + 0x7ff,
[all …]
/Linux-v5.10/arch/nios2/boot/dts/
D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_oneinit()
39 type = ~0; in gk104_top_oneinit()
40 inst = 0; in gk104_top_oneinit()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_oneinit()
45 switch (data & 0x00000003) { in gk104_top_oneinit()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_oneinit()
48 case 0x00000001: /* DATA */ in gk104_top_oneinit()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_oneinit()
50 info->addr = (data & 0x00fff000); in gk104_top_oneinit()
51 if (data & 0x00000004) in gk104_top_oneinit()
[all …]
/Linux-v5.10/arch/arm/mach-ep93xx/
Dts72xx.c71 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
72 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
83 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
84 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
86 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
101 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
110 .offset = 0,
129 .chip_offset = 0,
140 .start = 0, /* filled in later */
141 .end = 0, /* filled in later */
[all …]
/Linux-v5.10/drivers/net/wireless/broadcom/brcm80211/include/
Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.txt46 "p2u-N": where N ranges from 0 to one less than the total number of lanes
49 0: C0
64 - cell 0 specifies the bus and device numbers of the root port:
67 - cell 1 denotes the upper 32 address bits and should be 0
80 - 0x81000000: I/O memory region
81 - 0x82000000: non-prefetchable memory region
82 - 0xc2000000: prefetchable memory region
103 - pinctrl-0: phandle for the 'default' state of pin configuration.
146 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
147 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
[all …]
/Linux-v5.10/include/soc/fsl/qe/
Dqe.h32 #define MEM_PART_SYSTEM 0
38 QE_CLK_NONE = 0,
136 return 0; in cpm_muram_dma()
228 return 0; in qe_alive_during_sleep()
287 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
300 __be32 traps[16]; /* Trap addresses, 0 == ignore */
344 #define BD_STATUS_MASK 0xffff0000
345 #define BD_LENGTH_MASK 0x0000ffff
353 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
354 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
[all …]
/Linux-v5.10/arch/mips/include/asm/mips-boards/
Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/Linux-v5.10/drivers/macintosh/
Dwindfarm_pm91.c56 #define DBG(args...) do { } while(0)
82 #define FAILURE_FAN 0x01
83 #define FAILURE_SENSOR 0x02
84 #define FAILURE_OVERTEMP 0x04
152 if (hdr == 0) { in wf_smu_create_cpu_fans()
159 /* Get the FVT params for operating point 0 (the only supported one in wf_smu_create_cpu_fans()
167 tmax = 0x5e0000; /* 94 degree default */ in wf_smu_create_cpu_fans()
223 if (--st->ticks != 0) { in wf_smu_cpu_fans_tick()
250 if (temp > 0x4a0000) in wf_smu_cpu_fans_tick()
264 if (fan_cpu_main && wf_smu_failure_state == 0) { in wf_smu_cpu_fans_tick()
[all …]
/Linux-v5.10/arch/arm/boot/dts/
Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
Dsun8i-a23-a33.dtsi90 #size-cells = <0>;
92 cpu0: cpu@0 {
95 reg = <0>;
111 #clock-cells = <0>;
119 #clock-cells = <0>;
135 reg = <0x01c00000 0x30>;
142 reg = <0x01d00000 0x80000>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
150 reg = <0x000000 0x80000>;
[all …]
Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
200 size = <0x6000000>;
201 alloc-ranges = <0x40000000 0x10000000>;
215 reg = <0x01c00000 0x30>;
220 sram_a: sram@0 {
222 reg = <0x00000000 0xc000>;
[all …]
Dsun6i-a31.dtsi100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
[all …]
Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
183 size = <0x6000000>;
184 alloc-ranges = <0x40000000 0x10000000>;
210 #clock-cells = <0>;
217 #clock-cells = <0>;
233 #clock-cells = <0>;
240 #clock-cells = <0>;
247 #clock-cells = <0>;
[all …]
/Linux-v5.10/drivers/staging/rtl8712/
Drtl871x_mp.c26 pmp_priv->curr_rateidx = 0; in _init_mp_priv_()
27 pmp_priv->curr_txpoweridx = 0x14; in _init_mp_priv_()
30 pmp_priv->check_mp_pkt = 0; in _init_mp_priv_()
31 pmp_priv->tx_pktcount = 0; in _init_mp_priv_()
32 pmp_priv->rx_pktcount = 0; in _init_mp_priv_()
33 pmp_priv->rx_crcerrpktcount = 0; in _init_mp_priv_()
54 for (i = 0; i < NR_MP_XMITFRAME; i++) { in init_mp_priv()
64 return 0; in init_mp_priv()
70 return 0; in free_mp_priv()
93 u32 cmd32 = 0, val32 = 0; in fw_iocmd_read()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&ths 0>;
221 polling-delay-passive = <0>;
222 polling-delay = <0>;
[all …]
/Linux-v5.10/drivers/ata/
Dpata_macio.c44 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
74 #define IDE_TIMING_CONFIG 0x200
75 #define IDE_INTERRUPT 0x300
78 #define IDE_KAUAI_PIO_CONFIG 0x200
79 #define IDE_KAUAI_ULTRA_CONFIG 0x210
80 #define IDE_KAUAI_POLL_CONFIG 0x220
97 #define TR_133_PIOREG_PIO_MASK 0xff000fff
98 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
99 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
100 #define TR_133_UDMAREG_UDMA_EN 0x00000001
[all …]
/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dsm8150.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/Linux-v5.10/drivers/ide/
Dpmac.c95 #define IDE_TIMING_CONFIG 0x200
96 #define IDE_INTERRUPT 0x300
99 #define IDE_KAUAI_PIO_CONFIG 0x200
100 #define IDE_KAUAI_ULTRA_CONFIG 0x210
101 #define IDE_KAUAI_POLL_CONFIG 0x220
117 #define TR_133_PIOREG_PIO_MASK 0xff000fff
118 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
119 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
120 #define TR_133_UDMAREG_UDMA_EN 0x00000001
133 * register controls the UDMA timings. At least, it seems bit 0
[all …]
/Linux-v5.10/drivers/usb/gadget/udc/
Dudc-xilinx.c29 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */
30 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */
31 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */
32 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */
33 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */
34 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */
35 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */
36 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */
37 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */
38 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */
[all …]

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