Lines Matching +full:0 +full:x01e00000
46 "p2u-N": where N ranges from 0 to one less than the total number of lanes
49 0: C0
64 - cell 0 specifies the bus and device numbers of the root port:
67 - cell 1 denotes the upper 32 address bits and should be 0
80 - 0x81000000: I/O memory region
81 - 0x82000000: non-prefetchable memory region
82 - 0xc2000000: prefetchable memory region
103 - pinctrl-0: phandle for the 'default' state of pin configuration.
146 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
147 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
148 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
155 linux,pci-domain = <0>;
158 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
172 interrupt-map-mask = <0 0 0 0>;
173 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
175 nvidia,bpmp = <&bpmp 0>;
182 bus-range = <0x0 0xff>;
183 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
184 … 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
185 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
193 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
202 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
203 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
204 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
205 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
213 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
242 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",