95 #define IDE_TIMING_CONFIG	0x200
96 #define IDE_INTERRUPT		0x300
99 #define IDE_KAUAI_PIO_CONFIG	0x200
100 #define IDE_KAUAI_ULTRA_CONFIG	0x210
101 #define IDE_KAUAI_POLL_CONFIG	0x220
117 #define TR_133_PIOREG_PIO_MASK		0xff000fff
118 #define TR_133_PIOREG_MDMA_MASK		0x00fff800
119 #define TR_133_UDMAREG_UDMA_MASK	0x0003ffff
120 #define TR_133_UDMAREG_UDMA_EN		0x00000001
133  * register controls the UDMA timings. At least, it seems bit 0
138 #define TR_100_PIOREG_PIO_MASK		0xff000fff
139 #define TR_100_PIOREG_MDMA_MASK		0x00fff000
140 #define TR_100_UDMAREG_UDMA_MASK	0x0000ffff
141 #define TR_100_UDMAREG_UDMA_EN		0x00000001
144 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
154  *    of commented out code in Darwin. They leave it to 0, we do as
160 #define TR_66_UDMA_MASK			0xfff00000
161 #define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */
162 #define TR_66_UDMA_ADDRSETUP_MASK	0xe0000000 /* Address setup */
164 #define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */
166 #define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */
168 #define TR_66_MDMA_MASK			0x000ffc00
169 #define TR_66_MDMA_RECOVERY_MASK	0x000f8000
171 #define TR_66_MDMA_ACCESS_MASK		0x00007c00
173 #define TR_66_PIO_MASK			0x000003ff
174 #define TR_66_PIO_RECOVERY_MASK		0x000003e0
176 #define TR_66_PIO_ACCESS_MASK		0x0000001f
177 #define TR_66_PIO_ACCESS_SHIFT		0
187  * implementation afaik. The E bit appears to be set for PIO mode 0 and
190 #define TR_33_MDMA_MASK			0x003ff800
191 #define TR_33_MDMA_RECOVERY_MASK	0x001f0000
193 #define TR_33_MDMA_ACCESS_MASK		0x0000f800
195 #define TR_33_MDMA_HALFTICK		0x00200000
196 #define TR_33_PIO_MASK			0x000007ff
197 #define TR_33_PIO_E			0x00000400
198 #define TR_33_PIO_RECOVERY_MASK		0x000003e0
200 #define TR_33_PIO_ACCESS_MASK		0x0000001f
201 #define TR_33_PIO_ACCESS_SHIFT		0
206 #define IDE_INTR_DMA			0x80000000
207 #define IDE_INTR_DEVICE			0x40000000
210  * FCR Register on Kauai. Not sure what bit 0x4 is  ...
212 #define KAUAI_FCR_UATA_MAGIC		0x00000004
213 #define KAUAI_FCR_UATA_RESET_N		0x00000002
214 #define KAUAI_FCR_UATA_ENABLE		0x00000001
238     {   0,   0,   0 }
251     {   0,   0,   0 }
264     {   0,   0,   0 }
274     {   0, 180,  120 },	/* Mode 0 */
275     {   0, 150,  90 },	/*      1 */
276     {   0, 120,  60 },	/*      2 */
277     {   0, 90,   45 },	/*      3 */
278     {   0, 90,   30 }	/*      4 */
289 	{ 930	, 0x08000fff },
290 	{ 600	, 0x08000a92 },
291 	{ 383	, 0x0800060f },
292 	{ 360	, 0x08000492 },
293 	{ 330	, 0x0800048f },
294 	{ 300	, 0x080003cf },
295 	{ 270	, 0x080003cc },
296 	{ 240	, 0x0800038b },
297 	{ 239	, 0x0800030c },
298 	{ 180	, 0x05000249 },
299 	{ 120	, 0x04000148 },
300 	{ 0	, 0 },
305 	{ 1260	, 0x00fff000 },
306 	{ 480	, 0x00618000 },
307 	{ 360	, 0x00492000 },
308 	{ 270	, 0x0038e000 },
309 	{ 240	, 0x0030c000 },
310 	{ 210	, 0x002cb000 },
311 	{ 180	, 0x00249000 },
312 	{ 150	, 0x00209000 },
313 	{ 120	, 0x00148000 },
314 	{ 0	, 0 },
319 	{ 120	, 0x000070c0 },
320 	{ 90	, 0x00005d80 },
321 	{ 60	, 0x00004a60 },
322 	{ 45	, 0x00003a50 },
323 	{ 30	, 0x00002a30 },
324 	{ 20	, 0x00002921 },
325 	{ 0	, 0 },
330 	{ 930	, 0x08000fff },
331 	{ 600	, 0x0A000c97 },
332 	{ 383	, 0x07000712 },
333 	{ 360	, 0x040003cd },
334 	{ 330	, 0x040003cd },
335 	{ 300	, 0x040003cd },
336 	{ 270	, 0x040003cd },
337 	{ 240	, 0x040003cd },
338 	{ 239	, 0x040003cd },
339 	{ 180	, 0x0400028b },
340 	{ 120	, 0x0400010a },
341 	{ 0	, 0 },
346 	{ 1260	, 0x00fff000 },
347 	{ 480	, 0x00820800 },
348 	{ 360	, 0x00820800 },
349 	{ 270	, 0x00820800 },
350 	{ 240	, 0x00820800 },
351 	{ 210	, 0x00820800 },
352 	{ 180	, 0x00820800 },
353 	{ 150	, 0x0028b000 },
354 	{ 120	, 0x001ca000 },
355 	{ 0	, 0 },
360 	{ 120   , 0x00035901, },
361 	{ 90    , 0x000348b1, },
362 	{ 60    , 0x00033881, },
363 	{ 45    , 0x00033861, },
364 	{ 30    , 0x00033841, },
365 	{ 20    , 0x00033031, },
366 	{ 15    , 0x00033021, },
367 	{ 0	, 0 },
376 	for (i=0; table[i].cycle_time; i++)  in kauai_lookup_timing()
380 	return 0;  in kauai_lookup_timing()
418 		writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));  in pmac_ide_apply_timings()
436 		writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));  in pmac_ide_kauai_apply_timings()
529 		accessTicks = min(accessTicks, 0x1fU);  in pmac_ide_set_pio_mode()
531 		recTicks = min(recTicks, 0x1fU);  in pmac_ide_set_pio_mode()
538 		int ebit = 0;  in pmac_ide_set_pio_mode()
544 		accessTicks = min(accessTicks, 0x1fU);  in pmac_ide_set_pio_mode()
547 		recTicks = min(recTicks, 0x1fU);  in pmac_ide_set_pio_mode()
563 	printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",  in pmac_ide_set_pio_mode()
582 	rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);  in set_timings_udma_ata4()
583 	wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);  in set_timings_udma_ata4()
584 	addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);  in set_timings_udma_ata4()
592 	printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",  in set_timings_udma_ata4()
593 		speed & 0xf,  *timings);  in set_timings_udma_ata4()
596 	return 0;  in set_timings_udma_ata4()
614 	return 0;  in set_timings_udma_ata6()
632 	return 0;  in set_timings_udma_shasta()
643 	int cycleTime, accessTime = 0, recTime = 0;  in set_timings_mdma()
649 	switch(speed & 0xf) {  in set_timings_mdma()
650 		case 0: cycleTime = 480; break;  in set_timings_mdma()
717 		accessTicks = min(accessTicks, 0x1fU);  in set_timings_mdma()
718 		accessTicks = max(accessTicks, 0x1U);  in set_timings_mdma()
720 		recTicks = min(recTicks, 0x1fU);  in set_timings_mdma()
721 		recTicks = max(recTicks, 0x3U);  in set_timings_mdma()
731 		accessTicks = min(accessTicks, 0x1fU);  in set_timings_mdma()
735 		recTicks = min(recTicks, 0x1fU);  in set_timings_mdma()
742 		int halfTick = 0;  in set_timings_mdma()
748 		accessTicks = min(accessTicks, 0x1fU);  in set_timings_mdma()
752 		recTicks = min(recTicks, 0x1fU);  in set_timings_mdma()
768 	printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",  in set_timings_mdma()
769 		drive->name, speed & 0xf,  *timings);  in set_timings_mdma()
776 	int ret = 0;  in pmac_ide_set_dma_mode()
785 	tl[0] = *timings;  in pmac_ide_set_dma_mode()
790 			ret = set_timings_udma_ata4(&tl[0], speed);  in pmac_ide_set_dma_mode()
793 			ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);  in pmac_ide_set_dma_mode()
795 			ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);  in pmac_ide_set_dma_mode()
799 		set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);  in pmac_ide_set_dma_mode()
805 	*timings = tl[0];  in pmac_ide_set_dma_mode()
818 	unsigned int value, value2 = 0;  in sanitize_timings()
822 			value = 0x0a820c97;  in sanitize_timings()
823 			value2 = 0x00033031;  in sanitize_timings()
827 			value = 0x08618a92;  in sanitize_timings()
828 			value2 = 0x00002921;  in sanitize_timings()
831 			value = 0x0008438c;  in sanitize_timings()
834 			value = 0x00084526;  in sanitize_timings()
839 			value = 0x00074526;  in sanitize_timings()
842 	pmif->timings[0] = pmif->timings[1] = value;  in sanitize_timings()
857 	pmif->timings[0] = 0;  in pmac_ide_do_suspend()
858 	pmif->timings[1] = 0;  in pmac_ide_do_suspend()
864 		return 0;  in pmac_ide_do_suspend()
875 			    0);  in pmac_ide_do_suspend()
877 	return 0;  in pmac_ide_do_suspend()
890 		ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);  in pmac_ide_do_resume()
907 	return 0;  in pmac_ide_do_resume()
1026 	pmif->broken_dma = pmif->broken_dma_warn = 0;  in pmac_ide_setup_device()
1057 	pmif->aapl_bus_id =  bidp ? *bidp : 0;  in pmac_ide_setup_device()
1077 	pmif->hwif = host->ports[0];  in pmac_ide_setup_device()
1088 		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);  in pmac_ide_setup_device()
1094 		ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);  in pmac_ide_setup_device()
1120 	for (i = 0; i < 8; ++i)  in pmac_ide_init_ports()
1121 		hw->io_ports_array[i] = base + i * 0x10;  in pmac_ide_init_ports()
1123 	hw->io_ports.ctl_addr = base + 0x160;  in pmac_ide_init_ports()
1142 	if (macio_resource_count(mdev) == 0) {  in pmac_ide_macio_attach()
1150 	if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {  in pmac_ide_macio_attach()
1162 	if (macio_irq_count(mdev) == 0) {  in pmac_ide_macio_attach()
1167 		irq = macio_irq(mdev, 0);  in pmac_ide_macio_attach()
1169 	base = ioremap(macio_resource_start(mdev, 0), 0x400);  in pmac_ide_macio_attach()
1184 			pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);  in pmac_ide_macio_attach()
1190 	memset(&hw, 0, sizeof(hw));  in pmac_ide_macio_attach()
1197 	if (rc != 0) {  in pmac_ide_macio_attach()
1205 		macio_release_resource(mdev, 0);  in pmac_ide_macio_attach()
1220 	int rc = 0;  in pmac_ide_macio_suspend()
1225 		if (rc == 0)  in pmac_ide_macio_suspend()
1236 	int rc = 0;  in pmac_ide_macio_resume()
1240 		if (rc == 0)  in pmac_ide_macio_resume()
1288 	rbase = pci_resource_start(pdev, 0);  in pmac_ide_pci_attach()
1289 	rlen = pci_resource_len(pdev, 0);  in pmac_ide_pci_attach()
1292 	pmif->regbase = (unsigned long) base + 0x2000;  in pmac_ide_pci_attach()
1293 	pmif->dma_regs = base + 0x1000;  in pmac_ide_pci_attach()
1299 	memset(&hw, 0, sizeof(hw));  in pmac_ide_pci_attach()
1305 	if (rc != 0) {  in pmac_ide_pci_attach()
1323 	int rc = 0;  in pmac_ide_pci_suspend()
1328 		if (rc == 0)  in pmac_ide_pci_suspend()
1339 	int rc = 0;  in pmac_ide_pci_resume()
1343 		if (rc == 0)  in pmac_ide_pci_resume()
1401 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),	0 },
1402 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),	0 },
1403 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),	0 },
1404 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),	0 },
1405 	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),	0 },
1460 	int i = cmd->sg_nents, count = 0;  in pmac_ide_build_dmatable()
1480 			if (pmif->broken_dma_warn == 0) {  in pmac_ide_build_dmatable()
1485 			return 0;  in pmac_ide_build_dmatable()
1488 			unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;  in pmac_ide_build_dmatable()
1493 				return 0;  in pmac_ide_build_dmatable()
1498 			table->cmd_dep = 0;  in pmac_ide_build_dmatable()
1499 			table->xfer_status = 0;  in pmac_ide_build_dmatable()
1500 			table->res_count = 0;  in pmac_ide_build_dmatable()
1513 		memset(table, 0, sizeof(struct dbdma_cmd));  in pmac_ide_build_dmatable()
1522 	return 0; /* revert to PIO for this request */  in pmac_ide_build_dmatable()
1536 	if (pmac_ide_build_dmatable(drive, cmd) == 0)  in pmac_ide_dma_setup()
1541 		writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),  in pmac_ide_dma_setup()
1546 	return 0;  in pmac_ide_dma_setup()
1581 	/* verify good dma status. we don't check for ACTIVE beeing 0. We should...  in pmac_ide_dma_end()
1629 	timeout = 0;  in pmac_ide_dma_test_irq()
1633 		if ((status & FLUSH) == 0)  in pmac_ide_dma_test_irq()
1680 	if (dev == NULL || pmif->dma_regs == 0)  in pmac_ide_init_dma()
1698 	return 0;  in pmac_ide_init_dma()