Lines Matching +full:0 +full:x01e00000

71 #define TS72XX_NAND_CONTROL_ADDR_LINE	22	/* 0xN0400000 */
72 #define TS72XX_NAND_BUSY_ADDR_LINE	23	/* 0xN0800000 */
83 		bits = __raw_readb(addr) & ~0x07;  in ts72xx_nand_hwcontrol()
84 		bits |= (ctrl & NAND_NCE) << 2;	/* bit 0 -> bit 2 */  in ts72xx_nand_hwcontrol()
86 		bits |= (ctrl & NAND_ALE) >> 2;	/* bit 2 -> bit 0 */  in ts72xx_nand_hwcontrol()
101 	return !!(__raw_readb(addr) & 0x20);  in ts72xx_nand_device_ready()
110 		.offset		= 0,
129 		.chip_offset	= 0,
140 		.start		= 0,			/* filled in later */
141 		.end		= 0,			/* filled in later */
163 		ts72xx_nand_resource[0].start = start;  in ts72xx_register_flash()
164 		ts72xx_nand_resource[0].end = start + SZ_16M - 1;  in ts72xx_register_flash()
176 #define TS72XX_RTC_INDEX_PHYS_BASE	(EP93XX_CS1_PHYS_BASE + 0x00800000)
177 #define TS72XX_RTC_DATA_PHYS_BASE	(EP93XX_CS1_PHYS_BASE + 0x01700000)
180 	DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01),
181 	DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01),
194 #define TS72XX_WDT_CONTROL_PHYS_BASE	(EP93XX_CS2_PHYS_BASE + 0x03800000)
195 #define TS72XX_WDT_FEED_PHYS_BASE	(EP93XX_CS2_PHYS_BASE + 0x03c00000)
198 	DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01),
199 	DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01),
219 #define BK3_EN_SDCARD_PHYS_BASE         0x12400000
220 #define BK3_EN_SDCARD_PWR 0x0
221 #define BK3_DIS_SDCARD_PWR 0x0C
231 	pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__,  in bk3_mmc_spi_setpower()
258 		.bus_num		= 0,
259 		.chip_select		= 0,
287 #define TS73XX_FPGA_LOADER_BASE		0x03c00000
313 		.bus_num		= 0,
314 		.chip_select		= 0,
352 	.atag_offset	= 0x100,
365 	DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
382 		.offset	= 0x00000000,
383 		.size		= 0x01e00000,
386 		.offset	= 0x01e00000,
387 		.size		= 0x05f20000
390 		.offset	= 0x07d20000,
391 		.size		= 0x002e0000,
416 	.atag_offset	= 0x100,