29 #define XUSB_EP0_CONFIG_OFFSET		0x0000  /* EP0 Config Reg Offset */
30 #define XUSB_SETUP_PKT_ADDR_OFFSET	0x0080  /* Setup Packet Address */
31 #define XUSB_ADDRESS_OFFSET		0x0100  /* Address Register */
32 #define XUSB_CONTROL_OFFSET		0x0104  /* Control Register */
33 #define XUSB_STATUS_OFFSET		0x0108  /* Status Register */
34 #define XUSB_FRAMENUM_OFFSET		0x010C	/* Frame Number Register */
35 #define XUSB_IER_OFFSET			0x0110	/* Interrupt Enable Register */
36 #define XUSB_BUFFREADY_OFFSET		0x0114	/* Buffer Ready Register */
37 #define XUSB_TESTMODE_OFFSET		0x0118	/* Test Mode Register */
38 #define XUSB_DMA_RESET_OFFSET		0x0200  /* DMA Soft Reset Register */
39 #define XUSB_DMA_CONTROL_OFFSET		0x0204	/* DMA Control Register */
40 #define XUSB_DMA_DSAR_ADDR_OFFSET	0x0208	/* DMA source Address Reg */
41 #define XUSB_DMA_DDAR_ADDR_OFFSET	0x020C	/* DMA destination Addr Reg */
42 #define XUSB_DMA_LENGTH_OFFSET		0x0210	/* DMA Length Register */
43 #define XUSB_DMA_STATUS_OFFSET		0x0214	/* DMA Status Register */
46 #define XUSB_EP_CFGSTATUS_OFFSET	0x00	/* Endpoint Config Status  */
47 #define XUSB_EP_BUF0COUNT_OFFSET	0x08	/* Buffer 0 Count */
48 #define XUSB_EP_BUF1COUNT_OFFSET	0x0C	/* Buffer 1 Count */
50 #define XUSB_CONTROL_USB_READY_MASK	0x80000000 /* USB ready Mask */
51 #define XUSB_CONTROL_USB_RMTWAKE_MASK	0x40000000 /* Remote wake up mask */
54 #define XUSB_STATUS_GLOBAL_INTR_MASK	0x80000000 /* Global Intr Enable */
55 #define XUSB_STATUS_DMADONE_MASK	0x04000000 /* DMA done Mask */
56 #define XUSB_STATUS_DMAERR_MASK		0x02000000 /* DMA Error Mask */
57 #define XUSB_STATUS_DMABUSY_MASK	0x80000000 /* DMA Error Mask */
58 #define XUSB_STATUS_RESUME_MASK		0x01000000 /* USB Resume Mask */
59 #define XUSB_STATUS_RESET_MASK		0x00800000 /* USB Reset Mask */
60 #define XUSB_STATUS_SUSPEND_MASK	0x00400000 /* USB Suspend Mask */
61 #define XUSB_STATUS_DISCONNECT_MASK	0x00200000 /* USB Disconnect Mask */
62 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK	0x00100000 /* FIFO Buff Ready Mask */
63 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK	0x00080000 /* FIFO Buff Free Mask */
64 #define XUSB_STATUS_SETUP_PACKET_MASK	0x00040000 /* Setup packet received */
65 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK	0x00000200 /* EP 1 Buff 2 Processed */
66 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK	0x00000002 /* EP 1 Buff 1 Processed */
67 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK	0x00000100 /* EP 0 Buff 2 Processed */
68 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK	0x00000001 /* EP 0 Buff 1 Processed */
69 #define XUSB_STATUS_HIGH_SPEED_MASK	0x00010000 /* USB Speed Mask */
71 #define XUSB_STATUS_INTR_EVENT_MASK	0x01E00000
73 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK	0x0000FEFF
74 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */
75 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK	0x00000101
79 #define XUSB_EP_CFG_VALID_MASK		0x80000000 /* Endpoint Valid bit */
80 #define XUSB_EP_CFG_STALL_MASK		0x40000000 /* Endpoint Stall bit */
81 #define XUSB_EP_CFG_DATA_TOGGLE_MASK	0x08000000 /* Endpoint Data toggle */
85 #define XUSB_EP_NUMBER_ZERO		0	/* End point Zero */
87 #define XUSB_DMA_READ_FROM_DPRAM	0x80000000
88 #define XUSB_DMA_DMASR_BUSY		0x80000000 /* DMA busy */
89 #define XUSB_DMA_DMASR_ERROR		0x40000000 /* DMA Error */
94 #define XUSB_DMA_BRR_CTRL		0x40000000 /* DMA bufready ctrl bit */
96 #define SETUP_PHASE			0x0000	/* Setup Phase */
97 #define DATA_PHASE			0x0001  /* Data Phase */
98 #define STATUS_PHASE			0x0002  /* Status Phase */
100 #define EP0_MAX_PACKET		64 /* Endpoint 0 maximum packet length */
197 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
198 			  0x1600 };
266 	udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);  in xudc_wrstatus()
310  * Return: 0 on success, error code on failure
319 	int rc = 0;  in xudc_start_dma()
370  * Return: 0 on success, -EAGAIN if no buffer is free and error
408 		ep->curbufnum = 0;  in xudc_dma_send()
424  * Return: 0 on success, -EAGAIN if no buffer is free and error
457 		ep->curbufnum = 0;  in xudc_dma_receive()
473  * Return: 0 on success, -EAGAIN if no buffer is free.
483 	int rc = 0;  in xudc_eptxrx()
529 		ep->curbufnum = 0;  in xudc_eptxrx()
577  * Return: 0 if request is completed and -EAGAIN if not completed.
586 	u8 two_pkts = 0;  in xudc_read_fifo()
622 		return 0;  in xudc_read_fifo()
627 	case 0:  in xudc_read_fifo()
640 			xudc_done(ep, req, 0);  in xudc_read_fifo()
641 			return 0;  in xudc_read_fifo()
644 			two_pkts = 0;  in xudc_read_fifo()
655 		retval = 0;  in xudc_read_fifo()
667  * Return: 0 if request is completed and -EAGAIN if not completed.
678 	int is_last, is_short = 0;  in xudc_write_fifo()
689 	case 0:  in xudc_write_fifo()
696 				is_last = 0;  in xudc_write_fifo()
706 			xudc_done(ep, req, 0);  in xudc_write_fifo()
707 			retval = 0;  in xudc_write_fifo()
717 		retval = 0;  in xudc_write_fifo()
744  * Return: 0 for success and error value on failure
790 	return 0;  in xudc_ep_set_halt()
798  * Return: 0 for success and error value on failure
809 	ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);  in __xudc_ep_enable()
810 	/* Bit 3...0:endpoint number */  in __xudc_ep_enable()
811 	ep->epnumber = (desc->bEndpointAddress & 0x0f);  in __xudc_ep_enable()
821 		ep->is_iso = 0;  in __xudc_ep_enable()
825 		ep->is_iso = 0;  in __xudc_ep_enable()
833 		ep->is_iso = 0;  in __xudc_ep_enable()
846 	ep->buffer0ready = 0;  in __xudc_ep_enable()
847 	ep->buffer1ready = 0;  in __xudc_ep_enable()
848 	ep->curbufnum = 0;  in __xudc_ep_enable()
878 	return 0;  in __xudc_ep_enable()
886  * Return: 0 for success and error value on failure
920  * Return: 0 for success and error value on failure
952 	return 0;  in xudc_ep_disable()
990  * xudc_ep0_queue - Adds the request to endpoint 0 queue.
991  * @ep0: pointer to the xusb endpoint 0 structure.
994  * Return: 0 for success and error value on failure
1012 	req->usb_req.actual = 0;  in __xudc_ep0_queue()
1029 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);  in __xudc_ep0_queue()
1036 	return 0;  in __xudc_ep0_queue()
1040  * xudc_ep0_queue - Adds the request to endpoint 0 queue.
1041  * @_ep: pointer to the usb endpoint 0 structure.
1045  * Return: 0 for success and error value on failure
1069  * Return: 0 for success and error value on failure
1094 	_req->actual = 0;  in xudc_ep_queue()
1123 	return 0;  in xudc_ep_queue()
1131  * Return: 0 for success and error value on failure
1153 	return 0;  in xudc_ep_dequeue()
1163  * endpoint 0 enable should not be called by gadget layer.
1177  * endpoint 0 disable should not be called by gadget layer.
1227  * Return: 0 on success and error on failure
1254 	status = 0;  in xudc_wakeup()
1265  * Return: 0 always
1287 	return 0;  in xudc_pullup()
1300 	for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) {  in xudc_eps_init()
1307 						  (unsigned short) ~0);  in xudc_eps_init()
1331 		 * each endpoint is 0x10.  in xudc_eps_init()
1333 		ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10);  in xudc_eps_init()
1334 		ep->is_in = 0;  in xudc_eps_init()
1335 		ep->is_iso = 0;  in xudc_eps_init()
1336 		ep->maxpacket = 0;  in xudc_eps_init()
1353 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {  in xudc_stop_activity()
1373 	int ret = 0;  in xudc_start()
1391 	/* Set device address and remote wakeup to 0 */  in xudc_start()
1392 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_start()
1393 	udc->remote_wkp = 0;  in xudc_start()
1415 	/* Set device address and remote wakeup to 0 */  in xudc_stop()
1416 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_stop()
1417 	udc->remote_wkp = 0;  in xudc_stop()
1423 	return 0;  in xudc_stop()
1444 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {  in xudc_clear_stall_all_ep()
1480 		udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);  in xudc_startup_handler()
1482 		/* Set device address and remote wakeup to 0 */  in xudc_startup_handler()
1483 		udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_startup_handler()
1484 		udc->remote_wkp = 0;  in xudc_startup_handler()
1524 		udc->usb_state = 0;  in xudc_startup_handler()
1574 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_setaddress()
1578 	req->usb_req.length = 0;  in xudc_setaddress()
1580 	if (ret == 0)  in xudc_setaddress()
1595 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_getstatus()
1598 	u16 status = 0;  in xudc_getstatus()
1635 	if (ret == 0)  in xudc_getstatus()
1650 	struct xusb_ep *ep0	= &udc->ep[0];  in xudc_set_clear_feature()
1656 	int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0);  in xudc_set_clear_feature()
1672 				udc->remote_wkp = 0;  in xudc_set_clear_feature()
1719 	req->usb_req.length = 0;  in xudc_set_clear_feature()
1721 	if (ret == 0)  in xudc_set_clear_feature()
1737 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_handle_setup()
1792 	if (udc->driver->setup(&udc->gadget, &setup) < 0)  in xudc_handle_setup()
1798  * xudc_ep0_out - Processes the endpoint 0 OUT token.
1803 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_ep0_out()
1820 		xudc_done(ep0, req, 0);  in xudc_ep0_out()
1837 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);  in xudc_ep0_out()
1847  * xudc_ep0_in - Processes the endpoint 0 IN token.
1852 	struct xusb_ep *ep0 = &udc->ep[0];  in xudc_ep0_in()
1857 	u16 count = 0;  in xudc_ep0_in()
1885 		xudc_done(ep0, req, 0);  in xudc_ep0_in()
1917  * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler.
1919  * @intrstatus:	It's the mask value for the interrupt sources on endpoint 0.
1941  *		than endpoint 0.
1955 		ep->buffer0ready = 0;  in xudc_nonctrl_ep_handler()
1957 		ep->buffer1ready = 0;  in xudc_nonctrl_ep_handler()
2042  * Return: 0 for success and error value on failure
2071 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in xudc_probe()
2076 	irq = platform_get_irq(pdev, 0);  in xudc_probe()
2077 	if (irq < 0)  in xudc_probe()
2079 	ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0,  in xudc_probe()
2081 	if (ret < 0) {  in xudc_probe()
2106 	udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);  in xudc_probe()
2110 	/* Set device address to 0.*/  in xudc_probe()
2111 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);  in xudc_probe()
2129 	dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n",  in xudc_probe()
2133 	return 0;  in xudc_probe()
2143  * Return: 0 always
2151 	return 0;  in xudc_remove()