Lines Matching +full:0 +full:x01e00000
90 #size-cells = <0>;
92 cpu0: cpu@0 {
95 reg = <0>;
111 #clock-cells = <0>;
119 #clock-cells = <0>;
135 reg = <0x01c00000 0x30>;
142 reg = <0x01d00000 0x80000>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
150 reg = <0x000000 0x80000>;
157 reg = <0x01c02000 0x1000>;
166 reg = <0x01c03000 0x1000>;
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
178 #size-cells = <0>;
183 reg = <0x01c0c000 0x1000>;
193 #clock-cells = <0>;
202 #size-cells = <0>;
204 tcon0_in: port@0 {
205 reg = <0>;
220 reg = <0x01c0f000 0x1000>;
233 pinctrl-0 = <&mmc0_pins>;
236 #size-cells = <0>;
241 reg = <0x01c10000 0x1000>;
255 #size-cells = <0>;
260 reg = <0x01c11000 0x1000>;
274 #size-cells = <0>;
279 reg = <0x01c19000 0x0400>;
284 phys = <&usbphy 0>;
286 extcon = <&usbphy 0>;
310 reg = <0x01c1a000 0x100>;
321 reg = <0x01c1a400 0x100>;
331 reg = <0x01c20000 0x400>;
332 clocks = <&osc24M>, <&rtc 0>;
340 reg = <0x01c20800 0x400>;
342 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
452 reg = <0x01c20c00 0xa0>;
460 reg = <0x01c20ca0 0x20>;
467 reg = <0x01c21400 0xc>;
475 reg = <0x01c22800 0x100>;
482 reg = <0x01c28000 0x400>;
483 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
495 reg = <0x01c28400 0x400>;
508 reg = <0x01c28800 0x400>;
521 reg = <0x01c28c00 0x400>;
534 reg = <0x01c29000 0x400>;
547 reg = <0x01c2ac00 0x400>;
552 pinctrl-0 = <&i2c0_pins>;
555 #size-cells = <0>;
560 reg = <0x01c2b000 0x400>;
565 pinctrl-0 = <&i2c1_pins>;
568 #size-cells = <0>;
573 reg = <0x01c2b400 0x400>;
578 pinctrl-0 = <&i2c2_pins>;
581 #size-cells = <0>;
587 reg = <0x01c40000 0x10000>;
613 reg = <0x01c81000 0x1000>,
614 <0x01c82000 0x2000>,
615 <0x01c84000 0x2000>,
616 <0x01c86000 0x2000>;
624 reg = <0x01e00000 0x20000>;
634 #size-cells = <0>;
648 reg = <0x01e60000 0x10000>;
658 #size-cells = <0>;
660 be0_in: port@0 {
661 reg = <0>;
680 reg = <0x01e70000 0x10000>;
689 #size-cells = <0>;
691 drc0_in: port@0 {
692 reg = <0>;
711 reg = <0x01f00000 0x400>;
723 reg = <0x01f00c00 0x400>;
729 reg = <0x01f01400 0x200>;
733 #clock-cells = <0>;
742 #clock-cells = <0>;
751 #clock-cells = <0>;
777 reg = <0x01f01c00 0x300>;
782 reg = <0x01f02800 0x400>;
794 reg = <0x01f02400 0x400>;
797 pinctrl-0 = <&r_i2c_pins>;
802 #size-cells = <0>;
807 reg = <0x01f02c00 0x400>;
809 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
811 resets = <&apb0_rst 0>;
838 reg = <0x01f03400 0x400>;
844 pinctrl-0 = <&r_rsb_pins>;
847 #size-cells = <0>;