Lines Matching +full:0 +full:x01e00000
38 #define DAVINCI_PLL1_BASE 0x01c40800
39 #define DAVINCI_PLL2_BASE 0x01c40c00
40 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
42 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
43 #define SYSMOD_VDAC_CONFIG 0x2c
44 #define SYSMOD_VIDCLKCTL 0x38
45 #define SYSMOD_VPSS_CLKCTL 0x44
46 #define SYSMOD_VDD3P3VPWDN 0x48
47 #define SYSMOD_VSCLKDIS 0x6c
48 #define SYSMOD_PUPDCTL1 0x7c
60 #define DAVINCI_GPIO_BASE 0x01C67000
63 #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
64 #define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
67 #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
68 #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
74 #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
75 #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
76 #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
79 #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
80 #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
81 #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
82 #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
83 #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
86 #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
87 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000