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Searched refs:riscv (Results 1 – 25 of 117) sorted by relevance

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/Zephyr-latest/dts/riscv/qemu/
Dvirt-riscv32.dtsi9 #include <qemu/virt-riscv.dtsi>
14 riscv,isa = "rv32gc";
18 riscv,isa = "rv32gc";
22 riscv,isa = "rv32gc";
26 riscv,isa = "rv32gc";
30 riscv,isa = "rv32gc";
34 riscv,isa = "rv32gc";
38 riscv,isa = "rv32gc";
42 riscv,isa = "rv32gc";
Dvirt-riscv64.dtsi9 #include <qemu/virt-riscv.dtsi>
14 riscv,isa = "rv64gc";
18 riscv,isa = "rv64gc";
22 riscv,isa = "rv64gc";
26 riscv,isa = "rv64gc";
30 riscv,isa = "rv64gc";
34 riscv,isa = "rv64gc";
38 riscv,isa = "rv64gc";
42 riscv,isa = "rv64gc";
Dvirt-riscv.dtsi18 compatible = "riscv-virtio";
19 model = "riscv-virtio,qemu";
44 compatible = "qemu,riscv-virt", "riscv";
47 compatible = "riscv,cpu-intc";
58 compatible = "qemu,riscv-virt", "riscv";
61 compatible = "riscv,cpu-intc";
72 compatible = "qemu,riscv-virt", "riscv";
75 compatible = "riscv,cpu-intc";
86 compatible = "qemu,riscv-virt", "riscv";
89 compatible = "riscv,cpu-intc";
[all …]
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi19 compatible = "andestech,andescore-v5", "riscv";
23 riscv,isa = "rv32gc_xandes";
24 mmu-type = "riscv,sv32";
29 compatible = "riscv,cpu-intc";
36 compatible = "andestech,andescore-v5", "riscv";
40 riscv,isa = "rv32gc_xandes";
41 mmu-type = "riscv,sv32";
46 compatible = "riscv,cpu-intc";
53 compatible = "andestech,andescore-v5", "riscv";
57 riscv,isa = "rv32gc_xandes";
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi35 compatible = "sifive,s7", "riscv";
38 riscv,isa = "rv64imac_zicsr_zifencei";
42 compatible = "riscv,cpu-intc";
49 compatible = "sifive,u74", "riscv";
51 mmu-type = "riscv,sv39";
53 riscv,isa = "rv64gc";
56 compatible = "riscv,cpu-intc";
63 compatible = "sifive,u74", "riscv";
65 mmu-type = "riscv,sv39";
67 riscv,isa = "rv64gc";
[all …]
Driscv64-fu540.dtsi36 compatible = "sifive,e51", "riscv";
40 riscv,isa = "rv64imac_zicsr_zifencei";
42 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u54", "riscv";
52 mmu-type = "riscv,sv39";
56 riscv,isa = "rv64gc";
58 compatible = "riscv,cpu-intc";
67 compatible = "sifive,u54", "riscv";
69 mmu-type = "riscv,sv39";
73 riscv,isa = "rv64gc";
[all …]
/Zephyr-latest/dts/riscv/starfive/
Djh7110-visionfive-v2.dtsi23 compatible = "sifive,s7", "riscv";
26 riscv,isa = "rv64imac_zicsr_zifencei";
29 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u74", "riscv";
48 mmu-type = "riscv,sv39";
51 riscv,isa = "rv64imafdcg";
54 compatible = "riscv,cpu-intc";
61 compatible = "sifive,u74", "riscv";
73 mmu-type = "riscv,sv39";
76 riscv,isa = "rv64imafdcg";
[all …]
Dstarfive_jh7100_beagle_v.dtsi22 compatible = "starfive,rocket0", "riscv";
34 mmu-type = "riscv,sv39";
37 riscv,isa = "rv64gc";
42 compatible = "riscv,cpu-intc";
51 compatible = "starfive,rocket0", "riscv";
63 mmu-type = "riscv,sv39";
66 riscv,isa = "rv64gc";
71 compatible = "riscv,cpu-intc";
125 compatible = "riscv,machine-timer";
139 riscv,max-priority = <7>;
[all …]
/Zephyr-latest/dts/riscv/
Drenode_riscv32_virt.dtsi18 compatible = "renode,virt", "riscv";
21 riscv,isa = "rv32imac_zicsr_zifencei";
23 compatible = "riscv,cpu-intc";
54 compatible = "riscv,machine-timer";
67 riscv,max-priority = <1>;
68 riscv,ndev = <1023>;
78 riscv,max-priority = <1>;
79 riscv,ndev = <1023>;
/Zephyr-latest/dts/riscv/microchip/
Dmpfs.dtsi19 compatible = "sifive,e51", "riscv";
22 riscv,isa = "rv64imac_zicsr_zifencei";
24 compatible = "riscv,cpu-intc";
33 compatible = "sifive,u54", "riscv";
36 riscv,isa = "rv64gc";
38 compatible = "riscv,cpu-intc";
47 compatible = "sifive,u54", "riscv";
50 riscv,isa = "rv64gc";
52 compatible = "riscv,cpu-intc";
61 compatible = "sifive,u54", "riscv";
[all …]
Dmicrochip-miv.dtsi16 compatible = "microchip,miv", "riscv";
19 riscv,isa = "rv32ima_zicsr_zifencei";
21 compatible = "riscv,cpu-intc";
52 compatible = "riscv,machine-timer";
65 riscv,max-priority = <1>;
66 riscv,ndev = <31>;
/Zephyr-latest/boards/sifive/hifive_unleashed/support/
Dopenocd_hifive_unleashed.cfg10 set _CHIPNAME riscv
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
/Zephyr-latest/boards/sifive/hifive_unmatched/support/
Dopenocd_hifive_unmatched.cfg10 set _CHIPNAME riscv
14 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
15 target create $_TARGETNAME.1 riscv -chain-position $_TARGETNAME -coreid 1
16 target create $_TARGETNAME.2 riscv -chain-position $_TARGETNAME -coreid 2
17 target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
18 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
/Zephyr-latest/soc/litex/litex_vexriscv/
DCMakeLists.txt8 ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S
9 ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S
16 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
/Zephyr-latest/dts/riscv/lowrisc/
Dopentitan_earlgrey.dtsi20 compatible = "lowrisc,ibex", "riscv";
21 riscv,isa = "rv32imcb_zicsr_zifencei";
26 compatible = "riscv,cpu-intc";
48 compatible = "riscv,machine-timer";
77 riscv,max-priority = <7>;
78 riscv,ndev = <182>;
/Zephyr-latest/dts/riscv/niosv/
Dniosv-m.dtsi20 compatible = "intel,niosv", "riscv";
21 riscv,isa = "rv32ia_zicsr_zifencei";
27 compatible = "riscv,cpu-intc";
47 compatible = "riscv,machine-timer";
Dniosv-g.dtsi20 compatible = "intel,niosv", "riscv";
21 riscv,isa = "rv32ima_zicsr_zifencei";
27 compatible = "riscv,cpu-intc";
47 compatible = "riscv,machine-timer";
/Zephyr-latest/dts/riscv/efinix/
Dsapphire_soc.dtsi30 compatible = "efinix,vexriscv-sapphire", "riscv";
33 riscv,isa = "rv32ima_zicsr_zifencei";
37 compatible = "riscv,cpu-intc";
58 riscv,max-priority = <3>;
59 riscv,ndev = <32>;
69 compatible = "riscv,machine-timer";
/Zephyr-latest/boards/snps/nsim/arc_v/
Drmx1xx.dtsi11 compatible = "snps,av5rmx", "riscv";
15 riscv,isa = "rv32imac_zicsr_zifencei";
18 compatible = "riscv,cpu-intc";
41 compatible = "riscv,machine-timer";
/Zephyr-latest/boards/gd/gd32vf103c_starter/support/
Dopenocd.cfg5 # https://github.com/riscv/riscv-openocd OpenOCD fork.
/Zephyr-latest/boards/gd/gd32vf103v_eval/support/
Dopenocd.cfg5 # https://github.com/riscv/riscv-openocd OpenOCD fork.
/Zephyr-latest/soc/common/riscv-privileged/
DKconfig1 # Configuration options for riscv SOCs supporting the riscv privileged
/Zephyr-latest/boards/wch/ch32v003f4p6_dev_board/support/
Dopenocd.cfg3 set _CHIPNAME riscv
8 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
/Zephyr-latest/boards/wch/ch32v003evt/support/
Dopenocd.cfg4 set _CHIPNAME riscv
9 target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
/Zephyr-latest/tests/drivers/build_all/interrupt_controller/intc_plic/
Dapp.multi_instance.overlay10 riscv,max-priority = <7>;
11 riscv,ndev = <0x35>;

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